AD1981BJST-REEL 데이터 시트보기 (PDF) - Analog Devices

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AD1981BJST-REEL

AC ’97 SoundMAX® Codec

Analog Devices 

AD1981B

SPDIF Control Register (Index 3Ah)

Reg

No. Name D15 D14 D13

D12

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default

3Ah SPDIF V

Control

X SPSR1 SPSR0 L

CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h

Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the

exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is 0). This ensures that control and status

information start up correctly at the beginning of SPDIF transmission.

PRO

/AUD

COPY

PRE

CC[6:0]

L

SPSR[1:0]

V

Professional. 1 indicates professional use of channel status.

0 indicates consumer.

Non-Audio. 1 indicates data is non-PCM format.

0 data is PCM.

Copyright. 1 indicates copyright is asserted.

0 copyright is not asserted.

Pre-Emphasis. 1 indicates filter pre-emphasis is 50 µs/15 µs.

0 pre-emphasis is none.

Category Code. Programmed according to IEC standards, or as appropriate.

Generation Level. Programmed according to IEC standards, or as appropriate.

SPDIF Transmit Sample Rate.

SPSR[1:0] = 00 transmit sample rate = 44.1 kHz.

SPSR[1:0] = 01 Reserved.

SPSR[1:0] = 10 transmit sample rate = 48 kHz (reset default).

SPSR[1:0] = 11 not supported.

Validity. This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the

SPDIF transmitter to maintain connection during error or mute conditions.

V = 1 Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.

V = 0 Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error condition).

Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the

Validity flag low, marking both samples as valid.

–20–

REV. B

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