NCP1217A(2004) 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1217A
(Rev.:2004)
(Rev.:2004)
ON Semiconductor
NCP1217A Datasheet PDF : 18 Pages
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NCP1217, NCP1217A
Duty Cycle Typ = 74%
2.9 V
0V
19 k
Rcomp
+
L.E.B.
−
CS
Rsense
Latching Off the NCP1217
Total latched shutdown can easily be implemented
through a simple PNP bipolar transistor as depicted by
Figure 23. When OFF, Q1 is transparent to the operation.
When forward biased, the transistor pulls the Adj pin toward
VCC and permanently latches−off the IC as soon Vadj goes
above the latching level (typical 3.1 V). Figure 23 shows
how to wire the bipolar transistor to activate the latchoff. A
typical candidate for Q1 could be an MMBT3906 from
ON Semiconductor.
From
Setpoint
Figure 22. Inserting a Resistor in Series with the Current
Sense Information Brings Ramp Compensation
In the NCP1217, the ramp features a swing of 2.9 V with
a duty cycle max at 74%. Over a 65 kHz frequency, for
instance, it corresponds to a 254 mV/ms ramp. In our
FLYBACK design, let’s suppose that our primary
inductance Lp is 350 mH, delivering 12 V with a Np:Ns ratio
of 1:0.1. The OFF time primary current slope is thus given
by:
(Vout ) Vf)
Lp
·
Np
Ns
+
371
mAńms
or
37 mVńms
when
projected over an Rsense of 0.1 W, for instance. If we select
75% of the downslope as the required amount of ramp
compensation, then we shall inject 27 mV/ms. Our
internal compensation being of 254 mV/ms, the divider
ratio (divratio) between Rcomp and the 19 kW is 0.106.
A few lines of algebra to determine Rcomp:
19 k · divratio
(1−divratio)
+
2.26
kW.
VCC
Off
Q1
Rlimit
1
8
2
7
3
6
4
5
CVCC
Figure 23. A Simple Bipolar Transistor Totally
Disables the IC
VCC
VCCON = 12.8 V
The startup current source keeps the
device latched until reset occurs.
VCCmin = 7.6 V
VCClatch = 5.6 V
Drv
Adj
Reset level
Driver
Pulses
Latched−off
Time
Time
Default
adj level
Fault brings adj above latching level
Time
Figure 24. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches−Off the Output Pulses
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