PBA31308V2.02SLJYU 데이터 시트보기 (PDF) - Unspecified
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PBA31308V2.02SLJYU Datasheet PDF : 39 Pages
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Intel Public
UniStone
PBA 31308
General Device Overview
1.4
Pin Description
The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might
be removed/changed in future variants. All pins not listed below shall be not connected.
Table 1 Pin Description
Pin Symbol
No.
Input /
Output
A2 P1.6
I/O/OD
A3 RESET#
AI
A8 P1.5/
CLK32
I/O/OD
B1 P1.7/
WAKEUP_BT
I/O/OD
B2 P1.8/
I/O/OD
WAKEUP_HOST
B3 P1.0/
TMS
I/O/OD
B4 P1.4/
RTCK
I/O/OD
B5 ONOFF
I
B9 SLEEPX
I/O
C2 P0.9
I/O/OD
C3 JTAG#
I
C4 TRST#
D1 P0.10
D2 P0.8
D3 P1.1/
TCK
D4 P0.3/
PCMOUT
D5 P0.2/
PCMIN
D9 ANTENNA
E1 P0.12/
SDA0
E2 P0.13/
SCL0
E3 P1.3/
TDO/
SLOT_STATE
I
I/O/OD
I/O/OD
I/O/OD
I/O/OD
I/O/OD
AI/AO
I/O/OD
I/O/OD
I/O/OD
Supply Voltage During
Reset
Internal1
Z
Internal1
Input
Internal1
Input
Internal1
Internal1
Internal2
Internal2
VDDUART
Internal2
Internal2
PD/
Input
PD
PU1)
Z
-
PD
Z
PU
Internal2
Internal2
Internal2
Internal2
VDDPCM
VDDPCM
Internal2
Internal2
Internal2
PD
Z
PD
PU1)
Conf.
PD def.
Z
Inactive
PU
PU
Z
After
Reset
Z
Input
Input
PD/ Input
PD
PU1)
Z
-
H
Z
PU
PD
Z
PD
PU1)
Conf.
PD def.
Z
Inactive
PU
PU
Z
Function
Port 1.6
Hardware Reset
Port 1.5 or
LPM clock input (e.g.
32.768 kHz)
Port 1.7 or
Bluetooth wake-up signal
Port 1.8 or
Host wake-up signal
Port 1.0 or
JTAG interface
Port 1.4 or
JTAG interface
Turns off module completely
Sleep indication signal
Port 0.9
Mode selection Port 1:
0: JTAG
1: Port
JTAG interface
Port 0.10
Port 0.8
Port 1.1 or
JTAG interface
Port 0.3 or
PCM data out
Port 0.2 or
PCM data in
RF input/output single ended
Port 0.12 or
I2C data signal
Port 0.13 or
I2C clock signal
Port 1.3 or
JTAG interface or
WLAN coexistence interface
Product Overview
10
Revision 1.2, 2009-02-17
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