M-8880 데이터 시트보기 (PDF) - Clare Inc => IXYS

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M-8880

M-8880 DTMF Transceiver

Clare Inc => IXYS 

M-8880

Table 12 AC Characteristics (continued)

Parameter

Symbol

Min

Typ*

Max

Microprocessor interface (continued)

Data hold time (read)

f2 to valid data delay (read) (200 pF load)

tDHR

22

tDDR

—

—

—

—

150

Data setup time (write)

Data hold time (write)

Input capacitance, D0—D3

Output capacitance, IRQ/CP

DTMF clock

tDSW

45

tDHW

10

CIN

—

C/OUT

—

—

—

—

—

5

—

5

—

Crystal clock frequency

fC

3.5759

3.5795

3.5831

Clock input rise time (external clock)

tLHCL

—

—

110

Clock input fall time (external clock)

tHLCL

—

—

110

Clock input duty cycle (external clock)

DCCL

40

50

60

Capacitive load, OSC2

CLO

—

—

30

All voltages referenced to unless otherwise noted. VDD = 5.0 V ± 5%; VSS = 0 V; fC = 3.579545 MHz; TA = -40°C to +85°C

*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.

Notes:

1. dBm = decibels above or below a reference power of 1 mW into a 600 W load.

2. Digit sequence consists of all 16 DTMF tones.

3. Tone duration = 40 ms. Tone pause = 40 ms.

4. Nominal DTMF frequencies are used.

5. Both tones in the composite signal have an equal amplitude.

6. The tone pair is deviated by ± 1.5% ± 2 Hz.

7. Bandwidth limited (3 kHz) Gaussian noise.

8. The precise dial tone frequencies are 350 and 440 Hz (± 2%).

9. For an error rate of less than 1 in 10,000.

10. Referenced to the lowest amplitude tone in the DTMF signal.

11. Referenced to the minimum valid accept level.

Units

ns

ns

ns

ns

pF

pF

MHz

ns

ns

%

pF

Table 13 Electrical Characteristics - Gain Setting Amplifier

Parameter

Symbol

Min

Typ*

Max

Input leakage current (VSS £ VIN £ VDD)

Input resistance

IIN

—

100

—

RIN

—

10

—

Input offset voltage

Power supply rejection (1 KHz)

VOS

—

25

—

PSRR

—

60

—

Common mode rejection (-3.0 V £ VIN £ 3.0 V)

DC open-loop voltage gain

CMRR

—

60

—

AVOL

—

65

—

Unity gain bandwidth

BW

—

1.5

—

Output voltage swing (RL ³ 100 KΩ to VSS)

Maximum capacitive load, GS

Maximum resistive load, GS

VO

—

4.5

—

CL

—

100

—

RL

—

50

—

Common mode range (no load)

VCM

—

3.0

—

All voltages referenced to unless otherwise noted. VDD = 5.0 V; VSS = 0 V; TA = 25°C

*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.

Units

nA

MΩ

mV

dB

dB

dB

MHz

VPP

pF

KΩ

VPP

40-406-00012, Rev. G

Page 9

www.clare.com

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