M-8880 데이터 시트보기 (PDF) - Clare Inc => IXYS

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M-8880

M-8880 DTMF Transceiver

Clare Inc => IXYS 

M-8880 DTMF Transceiver

· Advanced CMOS technology for low power consump-

tion and increased noise immunity

· Complete DTMF transmitter/receiver in a single chip

· Standard 6500/6800 series microprocessor port

· Central office quality and performance

· Adjustable guard time

· Automatic tone burst mode

· Call progress mode

· Single +5 Volt power supply

· 20-pin DIP and SOIC packages

· 2 MHz microprocessor port operation

· Inexpensive 3.58 MHz crystal

· No continuous f2 clock required, only strobe

· Applications include: paging systems, repeater sys-

tems/mobile radio, interconnect dialers, PBX systems,

computer systems, fax machines, pay telephones,

credit card verification

The M-8880 is a complete DTMF Transmitter/Receiver that fea-

tures adjustable guard time, automatic tone burst mode, call

progress mode, and a fully compatible 6500/6800 microproces-

sor interface. The receiver portion is based on the industry stan-

dard M-8870 DTMF Receiver, while the transmitter uses a

switched-capacitor digital-to-analog converter for

low-distortion, highly accurate DTMF signaling. Tone bursts can

be transmitted with precise timing by making use of the auto-

matic tone burst mode. To analyze call progress tones, a call

progress filter can be selected by an external microprocessor.

Figure 1 Pin Diagram

Functional Description

M-8880 functions consist of a high-performance DTMF receiver

with an internal gain setting amplifier and a DTMF generator that

contains a tone burst counter for generating precise tone bursts

and pauses. The call progress mode, when selected, allows the

detection of call progress tones. A standard 6500/6800 series

microprocessor interface allows access to an internal status

register, two control registers, and two data registers.

Input Configuration

The input arrangement consists of a differential input opera-

tional amplifier and bias sources (VREF) for biasing the amplifier

inputs at VDD/2. Provisions are made for the connection of a

feedback resistor to the op-amp output (GS) for gain adjust-

40-406-00012, Rev. G

Figure 2 Block Diagram

Page 1

www.clare.com

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