Z80382 데이터 시트보기 (PDF) - Zilog

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Z80382

HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog 

Z80382/Z8L382

High-Performance Data Communications Processors

Zilog

DC CHARACTERISTICS (Continued)

Specifications apply over Standard Operating Conditions unless otherwise noted.

Table 1. Output Class Characteristics

Output Class(1)

Type

VOL Max.

VOH Min.

COUT Max.(2)

O

Totem Pole

0.4V @ IOL = 2.0 ma

VDD - 1.2V @ IOH = 200 mA

15 pF

Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF

3

Tri-State

0.4V @ IOL = 2.0 ma

VDD - 1.2V @ IOH = 200 mA

Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF

H

High Drive

0.4V max @ IOL = 16 mA,

2.4V min @ IOH = 5mA,

15 pF

Tri-State

VDD = 5V

VDD = 5V

Slew Rate = 0.33 V/ns min @ CLOAD = 50 pF

D

Open-Drain

0.4V max @ IOL = 16 mA

--

15 pF

Notes:

1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific output pins in each

class.

2. Applies to Output only or I/O.

Table 2. Input Class Characteristics

Input Class(1)

I

VIL Max.

(Z80382)

0.8V

VIL Max.

(Z8L382)

VIH Min.

(Z80382)

VIH Min.

(Z8L382)

0.6V

2.0V

2.0V

II = ±10 mA max, VI = 0 to 5V (includes leakage if I/O)

CIN = 5 pF max (if input only, see output type if I/O)

Minimum

Hysteresis

0.4V

Note: Inputs of this type include a weak-latch circuit, except that a register bit can disable those for pins PB7-0.

R

0.4V

0.4V

VDD - 0.6V

VDD - 0.3V

II = ±10 mA max, VI = 0 to 5V

CIN = 5 pF max

0.4V

Note: Inputs of this type except CLKI include a weak-latch circuit.

Notes:

1. The Pin Numbers and Input/Output Classifications table in the previous section identifies the specific input pins in each class.

8

PRELIMINARY

DS97Z382000

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