PCK2011DB 데이터 시트보기 (PDF) - Philips Electronics
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PCK2011DB Datasheet PDF : 11 Pages
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Philips Semiconductors
Direct Rambus™ Clock Generator
Preliminary specification
PCK2011
Table 4. AC DEVICE CHARACTERISTICS
Symbol Parameter
Min Max
tCYCLE
tJ
Clock cycle time
Cycle-to-cycle jitter at Clk/ClkB
Total jitter over 2, 3, or 4 clock cycles1
tSTEP
tERR,PD
Phase Aligner phase step size (at Clk/ClkB)
Phase Detector phase error for distributed loop Measured at PclkM-SynClkN (rising edges) (does not
include clock jitter)
tERR,SSC
PLL output Phase error when tracking SSC
DC
Output duty cycle over 10,000 cycles
tDC,ERR
Output cycle-to-cycle duty cycle error
tCR , tCF
Output rise and fall times (measured at 20% – 80% of output voltage)
tCR,CF
Difference between rise and fall times on a single device (20% – 80%)
VX, stop Output voltage during Clkstop (StopB = 0)
VX
Differential output crossing-point voltage
VCOS
Output voltage swing (p-p single-ended)
VOH
Output HIGH voltage
VOL
Output LOW voltage
ROUT
Output dynamic resistance (at pins)
IOZ
Output current during Hi-Z (S0 = 0, S1 = 1)
IOZ, stop Output current during ClkStop (StopB = 0)
Ipowerdown Current on powerdown (PwrDnB = 0)
IClkStop
Current on ClkStop (StopB = 0)
Inormal
Current on normal state (StopB = 1)
NOTE:
1. Output jitter specs measured at tCYCLE = 2.5ns.
2. VCOS = VOH – VOL
3. Rout = ∆VO/∆IO; this is defined at the output pins.
2.5
–
–
1
– 100
– 100
40%
–
250
–
1.1
1.3
0.4
–
1.0
12
–
–
–
3.75
60
100
–
100
100
60%
50
500
100
2.0
1.8
0.6
2.0
–
50
50
500
200
50
100
Unit
ns
ps
ps
ps
ps
ps
tCYCLE
ps
ps
ps
V
V
V
V
V
Ω
µA
µA
µA
mA
mA
Table 5. DRCG FUNCTIONS
REFCLK MULT0 MULT1
PLL
CLK/CLKB
MODE
S0
S1
S2
CLK CLKB
pin2
pin15 pin14 multiplier pins 20/18
pin 24 pin 23 pin 13 pin 20 pin 18
33
1
1
8
267
Normal
0
0
0
PAclk PAclk
50
0
1
6
300
Bypass
1
0
0
PLLclk PLLclk
50
1
1
8
400
Test
1
1
0
Refclk Refclk
67
0
0
4
267
Vendor Test A
0
0
1
–
–
67
0
1
6
400
Vendor Test B
1
0
1
–
–
100
1
0
8/3
267
Reserved
1
1
1
–
–
Output Test
0
1
x
Hi-Z
Hi-Z
1999 Jan 19
8
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