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5503DCR

Direct Conversion Receiver

TDK Corporation 

5503 DCR

Direct Conversion Receiver

FUNCTIONAL DESCRIPTION

AGC Amplifier

The 5503 RF input can be driven differentially or

single ended. The RFp and RFn inputs are self-

biasing and are designed to be driven from a 50

Ohm source. For single-ended operation, the RFn

pin should be AC coupled to analog ground. A gain

control input, AGC, provides a 22 dB gain variation

with 0V providing minimum gain and 4V providing

maximum gain.

I/Q Mixer

The AGC amplifier drives the RF port of two identical

double balanced mixers. The LO ports of these

mixers are driven from an on-chip quadrature

network.

Low Pass Filtering and Buffering

Following each mixer is a buffer amplifier for driving

an external passive low-pass filter. An external

series resistor connected to the IO1 or QO1 output

is used to provide the source match for the filter. A

second high impedance buffer amplifier is provided

(IIN or QIN) for additional gain and isolation after the

filter. The figure below shows a typical filter

designed for 20 Megasymbol per second operation:

Dual VCO

The 5503 uses two VCOs to cover the entire

specified tuning range. Both VCOs use nearly

identical architecture with the only difference being

slight design modifications to optimize the range of

operation. The lower range VCO requires an

external resonator that supports a tuning range of

950 to 1150 MHz. The higher range VCO requires a

similar resonator with inductor values designed to

support the range of 1100 to 1475 MHz. A typical

lumped-element resonator circuit incorporating

varactor tuning is shown in the following figure:

Ω

Ω

Ω

Ω

Note: A separate resonator circuit is required for

each oscillator

PLL Synthesizer

The synthesizer derives its reference from a source

which can be either an externally derived clock or an

external crystal coupled to the internal oscillator.

This source drives a programmable reference divider

with 15 preset divide ratios from 2 to 320. This

output provides the PLL reference by driving one

input of a phase/frequency detector. The VCO

output drives a divider chain incorporating a

selectable divide by two prescaler followed by a

variable modulus prescaler and divider. The divider

is programmed by a 17-bit control word. This divider

chain output drives the other input of the

phase/frequency detector.

Loop Filter

The phase/frequency detector provides two output

pairs, FILN/EON and FILP/EOP. The FILN/EON

outputs are used when the VCO has a positive gain

characteristic (increasing voltage yields increasing

frequency). The FILP/EOP outputs are used for a

negative VCO gain characteristic. Below is shown a

typical loop filter:

2

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