HSP48212 데이터 시트보기 (PDF) - Intersil
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HSP48212 Datasheet PDF : 9 Pages
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HSP48212
Pin Descriptions
NAME
PLCC PIN
CLK
9
DINA0-11
DINB0-11
M0-11
29-31
33-34
36-38
40-43
10-15, 17
19-23
62-65
67-68
2-7
TC
28
RND0-1
24-25
MIXEN
8
LD
27
DEL
26
BYPASS
61
DOUT0-12
OE
VCC
GND
59-56
54-53
51-50
48-44
60
32, 49, 66
16, 39, 55
TYPE
I
I
DESCRIPTION
Clock Input. All signal pins are synchronous with respect to this clock except LD, DEL, OE, and BY-
PASS.
Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge
of CLK.
I
Input Data Bus. Provides data to the Mixer from one video source. Synchronous to the rising edge
of CLK.
I
Mix Input Bus. The range of M is from 0 to 1. The number format is unsigned, with one bit position
to the left of the binary point. If a value greater than 1 is placed on this bus, the internal circuitry will
saturate M to 1, i.e, anytime the MSB is 1, the internal value defaults to 1.00000000000; synchro-
nous to the rising edge of CLK.
I
Specifies the number format of the input data busses DINA and DINB. 1 = unsigned, 0 = 2’s com-
plement. The signal has the same number of latency stages as the incoming data. Therefore, the
number format affects the incoming data but not the data in the internal pipeline stages. Synchro-
nous to the rising edge of CLK.
I
Specifies the number of significant bits on the output bus. 00 = 8-bit, 01 = 10-bit,
10 = 12-bit, 11 = 13-bit. Rounding is performed by adding a binary 1 to the bit position to the right of
the desired LSB. The remaining bits are forced to zero. These control signals have the same number
of latency stages as the incoming data. Therefore, the output round format does not take effect until
the current data has propagated to the output. Synchronous to the rising edge of CLK.
I
Mix Enable. This pin is used to disable the clock signal which samples the Mix input. When MIXEN
= 1, the M0-11 bus is sampled by the rising edge of CLK. When MIXEN = 0, the M0-11 bus is ignored
and the previously stored value of M0-11 is used. Synchronous to the rising edge of CLK.
I
Asynchronous Load Pin. LD is used to load the delay control registers. The delay control word is
loaded serially from LSB to MSB. This signal drives the clock input to a
15-bit serial shift register. Each LD cycle, the data is transferred through the register bank on the
rising edge of LD In order to load the delay control word, the user must supply exactly 15 LD pulses.
I
Delay Input. This is the serial input data that is sampled by the rising edge of LD. It is the input to the
first stage of the 15-bit serial shift register which contains the delay control word. Synchronous to the
rising edge of LD.
I
Allows user to disable (bypass) the LD interface and use the default delay paths. When BYPASS =
1, the delay control word is forced to all 0’s and no extra delays are included in the paths. When BY-
PASS = 0, the delay control word must be initialized using the LD/DEL interface in order for the chip
to give predictable results. This pin is asynchronous and is not intended to change states during op-
eration.
O
Output Data Bus. The data on this bus reflects the results of the equation:
2x[AxM + Bx(1-M)]. The number format of the output is either 2’s complement or unsigned depend-
ing on the value of the TC signal during data input. The representation of DOUT is also dependent
on the value sampled on RND0-1 during data input.
(See RND0-1 and TC pin description).
I
Output Enable. Asynchronous input which takes effect immediately following a transition. When OE =
0 the DOUT bus is driving, when OE = 1 the DOUT bus is not driven (floating).
I
5V power supply. There are 3 VCC pads.
I
0V power supply. There are 3 GND pads.
3
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