HSP50306(2004) 데이터 시트보기 (PDF) - Intersil
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HSP50306 Datasheet PDF : 8 Pages
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HSP50306
SPECIFICATION
BER
Acquisition Time
Carrier Loop Bandwidth
Bit Sync Loop Bandwidth
Throughput Delay
TABLE 1. PERFORMANCE SPECIFICATIONS
PERFORMANCE
Better than 1.0 x 10-9 with specified input signal characteristics. (See Figure 1.)
Acquisition within 0.1s from applying an input signal with the specified characteristics.
10kHz
3kHz
Less than 6 output bit times.
PARAMETER
Carrier Frequency
Bit Rate
TABLE 2. INPUT SIGNAL CHARACTERISTICS (NOTE 1)
SPECIFICATION
10.7 x 106 ±40kHz.
2.048 x 106 ±0.01%.
Modulation Format
QPSK w/differential encoding specified as:
00: 0° phase change
01: -90° phase change
10: +90° phase change
11: 180° phase change (Note 2)
Filtering
Square root of raised cosine matched filtering (α = 0.4).
Input RMS Signal Level
Set input p-p signal to full scale on the A/D converter.
Input Data Format
Input Clock Frequency
6 bits, offset binary.
26.97MHz ±0.015% (Note 3) for -27; 25.6MHz ±0.015% for -25.
SINAD
>25.5dB SNR (thermal (AWGN)), >28dB (adjacent channel interference).
Multipath Distortion
Total energy in multipath distortion -10dBc
>95% of multipath energy within 2µs from main path. If the multipath changes rapidly, the bit error rate
may exceed the above specification until the equalizer has readjusted.
NOTES:
1. All frequencies are relative to the input clock frequency. For example, the bit rate is actually ~0.075936 * fCLK. The frequencies provided
in this document are only valid for a 26.97MHz or 25.6MHz clock.
2. Each pair of input bits is encoded into a phase change relative to the previous symbol. In the HSP50306, the symbol to symbol phase
change is decoded into the transmitted bit pair which is multiplexed into the output data stream.
3. While the device is static CMOS and can be clocked down to close to DC, the specified range indicates the accuracy needed to maintain
the data rate inside the bit sync tracking loop bandwidth assuming 50ppm tx and 100ppm rx crystal accuracies.
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