HSP50306(2004) 데이터 시트보기 (PDF) - Intersil

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HSP50306
(Rev.:2004)

Digital QPSK Demodulator

Intersil 

Pinout

HSP50306

16 LEAD SOIC

TOP VIEW

AGCOUT 1

CLKOUT 2

DATAOUT 3

LOCK 4

RESET 5

TEST 6

CLKIN 7

GND 8

16 VCC

15 ADCLK

14 DIN0

13 DIN1

12 DIN2

11 DIN3

10 DIN4

9 DIN5

Pin Description

NAME SOIC PIN

VCC

16

GND

8

CLKIN

7

DIN (5:0)

9-14

ADCLK

15

AGCOUT

1

DATAOUT

3

CLKOUT

2

LOCK

4

RESET

5

TEST

6

TYPE

DESCRIPTION

-

+5V Power Supply

-

Ground

I

Clock input. This is the processing clock for the part. All timing is derived from this clock.

I

I.F. input samples from the A/D converter. These bits interpreted as offset binary format. DIN5 is the

MSB. If fewer than 6 bits are used, the bits from the A/D should be connected to the MSBs of the

input and the unused LSBs grounded.

O This output clock is the clock for the A/D converter.

O This output indicates whether the magnitude of the input samples are above or below the expected

level. This output is provided as an error detector for an external AGC loop. The output is low when

the input is greater than nominal, and high when the input is lower than nominal.

O This is the recovered data.

O This is the recovered clock.

O This signal indicates that the carrier tracking loop is locked and data on the DOUT pin should be valid.

I

This input is provided to for initialization and test. Active low.

I

This input is provided for test. Pull high for normal operation.

2

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