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WT62P1

Digital monitor controller with USB function

Weltrend Semiconductor 

WT62P1

Data Sheet Rev. 1.01

I/O Port

I/O Port A

Pin PA0 and PA1 are shared with DDC interface SDA1 and SCL1 When ENDDC bit is “ 0” , These two

pins becomes I/O port. If PA0OE bit is set, Pin PA0 is an open-drain output. If PA0OE is cleared, Pin

PA0 is an input pin with no internal pull-up resistor. The operation of PA1 is same as PA0. Fig. 2 Shows

the structure of PA0.

INTERNAL_DATA_BUS

DATA[0]

D

Q PA0OE

PA0

WRITE_PA_CTRL

RESET

C QN

R

DATA[0]

D

Q PA0

WRITE_PA_DATA C QN

R

RESET

READ_PA_DATA

DATA[0]

Fig.2 Structure of PA0 and PA1

Pin PA2 to PA6 are shared with PWM output. When corresponding EPWMx bit is “ 0” , the pin is I/O port.

If PAxOE bit is set, it is a push-pull type output. If PAxOE bit is cleared, it is an input pin with internal

pull-up resistor.

Pin PA7 is shared with PWM13 output and clamp pulse output. When both EPWM13 bit and ENCLP bit

are “ 0” , this pin becomes I/O port. If PA7OE bit is set, it is a push-pull type output. If PA7OE bit is

cleared, it is an input pin with internal pull-up resistor.

INTERNAL_DATA_BUS

DATA[2]

D

Q PA2OE

WRITE_PA_CTRL C QN

R

PA2

RESET

DATA[2]

D

Q PA2

WRITE_PA_DATA C QN

R

RESET

READ_PA_DATA

DATA[2]

Fig.3 Structure of PA2

Weltrend Semiconductor, Inc.

Page 7

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