WT62P1 데이터 시트보기 (PDF) - Weltrend Semiconductor

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WT62P1

Digital monitor controller with USB function

Weltrend Semiconductor 

WT62P1

Data Sheet Rev. 1.01

FUNCTIONAL DESCRIPTION

CPU

8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit.

The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher

priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.

Please refer the 6502 reference menu for more detail.

RAM

512 bytes RAM. Address is located from $0080h to $00FFh and $0180h to $02FFh.

RAM from $0200h to $027Fh and $0280h to $02FFh can be disabled individually to emulate different

RAM size IC. (see Register $0FFFh)

ROM

32768 bytes flash memory for program. Address is located from $8000h to $FFFFh.

The following addresses are reserved for special purpose :

$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.

$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.

$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.

System Reset

$0000h

:

Registers

$003Fh

$0040h

:

Reserved

$007Fh

$0080h

:

128 bytes RAM

$00FFh

$0100h

:

Reserved

$017Fh

$0180h

:

384 bytes RAM

$02FFh

$0300h

:

Reserved

$0FFEh

$0FFFh Configuration Register

$1000h

:

Reserved

$7FFFh

$8000h

:

:

Flash ROM

:

$FFFFh

There are four reset sources of this controller. Fig.1 shows the block diagram of reset logic.

Weltrend Semiconductor, Inc.

Page 5

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