HSP50016GC-52 데이터 시트보기 (PDF) - Intersil

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HSP50016GC-52

Digital Down Converter

Intersil 

HSP50016

Local Oscillator

Signal data clocked into the DATA0-15 input of the DDC is

multiplied by a quadrature sinusoid in the Mixer Section (see

Figure 1). The data input to the DDC is a 16-bit real data

stream which is sampled on the rising edges of CLK. It can

be in two's complement or offset binary format.

The input data is passed to a mixer, which is composed of

two real multipliers. One of these multiplies the input data

samples by the in-phase (cosine) component of the

quadrature sinusoid, and the other multiplies the input data

samples by the quadrature (sine) component. The in-phase

and quadrature data paths are designated I and Q

respectively. The sine and cosine are generated in the local

oscillator as shown in Figure 1.

The local oscillator is programmed to produce a quadrature

sinusoid with programmable frequency and phase. The

frequency can be constant (Continuous Wave - CW), linearly

increasing (up chirp), linearly decreasing (down chirp), or

linear up/down chirp. The initial phase of the waveform is set

by the phase offset.

The phase, frequency and chirp limits of the quadrature

sinusoid are controlled by the Phase Generator (Figure 2).

The output of the Phase Generator is an 18-bit phase word

that represents the current phase angle of the complex

sinusoid. The Phase Generator automatically increments the

phase angle by a preprogrammed amount on every rising

edge of CLK. Stepping the output phase from 0 through full

scale (218 - 1) steps the phase angle of the quadrature

sinusoid from 0 to (-2+2-17)π radians. NOTE: The phase is

stepped in a clockwise (decreasing) direction to support

down conversion. The frequency of the complex sinusoid is

determined by the number of clocks needed for the phase to

step though its full range of 2π radians. The required phase

increment for a given local oscillator frequency is calculated by:

Phase Increment = INT [(fC ⁄ fS) 233]H

fC = (Phase Incr) fS 2–33; 0 < fC < fS/2

(EQ. 1)

where:

fC is the desired local oscillator frequency

fS is the input sampling frequency

Phase Increment is the Control Word Value (in Hex)

There are five parameters which control the Phase Generator:

Phase offset, minimum phase increment, maximum phase

increment, delta phase increment and Mode Control. These

values are programmed via Control Words 2, 3, and 4. Mode

Control is used to select the function of the other parameters.

The phase offset is the initial setting of the phase word going

to the SIN/COS Generator. Subsequent phases of the

sinusoid are calculated relative to this offset. The minimum

phase increment has two mode dependent functions: when

the SIN/COS Generator is forming a CW waveform, the

minimum phase increment is the phase step taken on every

clock. When the SIN/COS Generator is producing a chirped

sinusoid, the minimum phase increment is the smallest

phase step taken. Maximum phase increment is only used

during Chirped Modes; it is the largest allowable phase

increment. During Chirp Modes, the delta phase increment

is the difference between successive phase increments.

The four phase parameters are stored in their respective

registers in the Phase Generator. The Phase Register stores

the current phase angle. On the first clock following the

deassertion of RESET, the 18 MSBs of the Phase Register

are loaded from the Phase Offset Register. On every rising

edge of CLK thereafter, the output of the Phase Increment

Register is subtracted from the 32 LSBs of the current

phase. The 33-bit difference is stored back in the Phase

Register on the next CLK. The 18 most significant bits of the

Phase Register form the phase word, which is the input to

the SIN/COS Generator.

Figure 3 gives a graphic representation of the phase

parameters for the CW case. To understand their

interrelationships, the phase should be visualized as the

angle of a rotating vector. When the local oscillator in the

DDC is programmed to generate a CW waveform, the

multiplexers are configured so that the Minimum Phase

Increment is stored in the Phase Increment Register; this

value is subtracted from the output of the Phase Register on

every CLK and the difference becomes the new Phase

Register value. The Delta Phase Increment and Maximum

Phase Increment are ignored when generating a CW.

±180o

STARTING PHASE

+90o

(0)

(1)

θINCR

θOFFSET

θINCR

(2)

(3)

θINCR

0o

(4)

(5)

θINCR

-90o

θINCR

FIGURE 3. PHASE WORD PARAMETERS FOR CW CASE

In Up Chirp Mode the local oscillator generates a signal

with a linearly increasing frequency (Figure 4A). The Phase

Increment Register is initially loaded with the minimum

Phase Increment value; on every clock, the contents of the

Phase Increment Register is subtracted from the current

output of the Phase Register. Simultaneously, the Delta

3-203

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