HSP50016GC-52 데이터 시트보기 (PDF) - Intersil

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HSP50016GC-52

Digital Down Converter

Intersil 

DDC Functional Block Diagram

MIXER

SECTION

HDF

SCALING

SECTION MULTIPLIER

FIR SECTION

†INPUT

FORMAT

SHIFTER

17

HDF

18

DATA

17 RAM

MULTIPLIER/

18

ACCUMULATOR

CLK

R

17

†HDF CLK

COEFFICIENT

CLK

SHIFT

†HDF

ROM

22

4R

DECIMATION

COUNTER PRELOAD (DCP)

SHIFT

REGISTER

I

CLKSER = IQCLK

DATA0-15

16

INPUT

REGISTER

SHIFTER

COS

17

SIN 17

HDF

18

DATA

17 RAM

MULTIPLIER/

18 ACCUMULATOR

FORMATTER

SHIFT

REGISTER

Q

†WAIT FOR RAM FULL

†OUTPUT FORMAT

(PARALLEL

†MIN PHASE INCR

†DELTA PHASE INCR

†PHASE OFFSET

SIN/COS

GENERATOR

PHASE WORD 18

PHASE

GENERATOR

SCALE

FACTOR

†SCALING

MULTIPLIER

GAIN

†TIME SLOT LENGTH

†NUMBER OF OUTPUT BITS

†OUTPUT SENSE

†I FOLLOWED BY Q

†TIME SLOT NUMBER

†IQCLK POLARITY

†IQCLK DUTY CYCLE

†IQCLK DURATION

TO SERIAL

CONVERTER

AND BUFFER)

†MAX PHASE INCR

†IQCLK THREE-STATE CTL

†MODE

LOCAL OSCILLATOR

†IQSTRB POLARITY

†IQSTRB LOCATION

IQSTB

†IQSTRB THREE-STATE CTRL

IQSTRT

†I POLARITY AND THREE-STATE CTRL

0

†Q POLARITY AND THREE-STATE CTRL

†IQ CLK RATE

IQCLK

CS

†TEST ENABLE AND CONTROL SIGNALS

CSTB

CDATA

CCLK

CLK

RESET

DECODER

DQ

DQ

1

1

2

2

†CONTROL

PARAMETERS

7

7

CONTROL CONTROL

BUFFERS REGISTERS

TCLK

TMS

TDI

TRST

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM

IEEE 1149.1

TEST ACCESS PORT

TDO

† Indicates parameters from control registers.

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