WM9709 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM9709

AC-link Interface Audio DAC

Wolfson Microelectronics plc 

Production Data

RESETB

SDATAOUT

SDATAIN,

BITCLK

tsetup2rst

toff

Hi-Z

WM9709

Figure 4 ATE Test Mode Timing

PARAMETER

Setup to trailing edge of RESETB

(also applies to SYNC)

Rising edge of RESETB to Hi-Z

delay

Notes:

SYMBOL

Tsetup2rst

Toff

MIN

15.0

-

TYP

-

-

MAX

-

25.0

UNIT

nS

nS

1. All WM9709 signals are normally low through the trailing edge of RESETB. Bringing

SDATAOUT high for the trailing edge of RESETB causes WM9709’s AC-link outputs to go high

impedance, which is suitable for ATE in circuit testing.

2. A vendor specific internal test mode can be entered by bringing SYNC high for the trailing edge

of RESETB. This mode has no effect on WM9709 AC-link output signal levels.

3. Once either of the two test modes have been entered, WM9709 must be issued another

RESETB with all AC-link signals low to return to the normal operating mode.

SIGNAL RISE AND FALL TIMES

triseCLK

BITCLK

triseSYNC

SYNC

triseDIN

SDATAIN

triseDOUT

SDATAOUT

tfallCLK

tfallSYNC

tfallDIN

tfallDOUT

Figure 5 Signal Rise and Fall Times (50pF external load)

w

PD Rev 1.3 February 2003

7

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