WM9709 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM9709 Datasheet PDF : 18 Pages
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WM9709
CLOCK SPECIFICATIONS
BITCLK
SYNC
tCLK_HIGH
tCLK_PERIOD
tSYNC_HIGH
tCLK_LOW
tSYNC_LOW
tSYNC_PERIOD
Production Data
Figure 2 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
BITCLK frequency
BITCLK period
BITCLK output jitter
BITCLK high pulse width
BITCLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
SYMBOL
MIN
tCLK_PERIOD
tCLK_HIGH
tCLK_LOW
32.56
32.56
tSYNC_PERIOD
tSYNC_HIGH
tSYNC_LOW
DATA OUTPUT AND INPUT TIMES
tCO
tSETUP
TYP
12.288
81.4
40.7
40.7
48.0
20.8
1.3
19.5
MAX
750
48.84
48.84
BITCLK
SYNC,
SDATAOUT,
SDATAIN
Figure 3 Data Output and Input Timing
tHOLD
UNIT
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
PARAMETER
Setup to falling edge of BITCLK
Hold from falling edge of
BITCLK
Output Valid Delay from rising
edge of BITCLK
SYMBOL
tSETUP
tHOLD
tCO
MIN
10.0
10.0
TYP
MAX
15.0
UNIT
ns
ns
ns
ATE IN CIRCUIT TEST MODE
When the WM9709 is placed in the ATE test mode, its digital AC-link outputs (BITCLK and
SDATAIN) are driven to a high impedance state. This allows ATE in circuit testing of the WM9709.
w
PD Rev 1.3 February 2003
6
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