WM8580 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8580

Multichannel CODEC with S/PDIF Transceiver

Wolfson Microelectronics plc 

Production Data

WM8580

The MSB of the left channel of the output data changes on the first falling edge of BCLK following a

low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel

data is contiguous with the left channel data.

Figure 19 DSP Mode A Timing Diagram – PAIF/SAIF Transmitter Data

DSP MODE B

In DSP Mode B, the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a

LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 and 3

follow as shown in Figure 20.

Figure 20 DSP Mode B Timing Diagram – PAIF Receiver Input Data

For the SAIF Receiver, only stereo information is processed.

Figure 21 DSP Mode B Timing Diagram - SAIF Receiver Input Data

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PD Rev 4.3 August 2007

27

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