WM8580 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8580 Datasheet PDF : 97 Pages
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Production Data
WM8580
REGISTER BIT LABEL
ADDRESS
R9
PAIF 1
5 PAIFRX
MS
09h
R10
PAIF 2
5 PAIFTX
MS
0Ah
R11
5 SAIFMS
SAIF 1
0Bh
Table 12 Master Mode Registers
DEFAULT
0
0
0
DESCRIPTION
PAIF Receiver Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
PAIF Transmitter Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
SAIF Master/Slave Mode Select:
0 = Slave Mode
1 = Master Mode
The frequency of a master mode LRCLK is dependant on system clock and the RATE register
control bits. Table 13 shows the settings for common sample rates and system clock frequencies.
SAMPLING RATE
(LRCLK)
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192kHz
128fs
RATE =000
4.096
5.6448
6.144
11.2896
12.288
22.5792
24.576
192fs
RATE =001
6.144
8.467
9.216
16.9344
18.432
33.8688
36.864
MCLK CLOCK FREQUENCY (MHZ)
256fs
384fs
512fs
768fs
1152fs
RATE =010 RATE =011 RATE =100 RATE =101 RATE =110
8.192
12.288
16.384
24.576
36.864
11.2896
16.9344
22.5792
33.8688 Unavailable
12.288
18.432
24.576
36.864 Unavailable
22.5792
33.8688 Unavailable Unavailable Unavailable
24.576
36.864 Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable Unavailable
Unavailable Unavailable Unavailable Unavailable Unavailable
Table 13 Master Mode MCLK / LRCLK Frequency Selection
REGISTER
BIT
ADDRESS
R9
2:0
PAIF 1
09h
R10
2:0
PAIF 2
0Ah
R11
2:0
SAIF 1
0Bh
LABEL
PAIFRX_RATE
[2:0]
PAIFTX_RATE
[2:0]
SAIF_RATE
[2:0]
Table 14 Master Mode RATE Registers
DEFAULT
DESCRIPTION
010
Master Mode MCLK/LRCLK
Ratio:
000 = 128fs
010
001 = 192fs
010 = 256fs
011 = 384fs
010
100 = 512fs
101 = 768fs
110 = 1152fs
In master mode, the BCLKSEL register controls the number of BCLKs per LRCLK. If the
MCLK:LRCLK ratio is 128fs or 192fs and BCLKSEL = 10, BCLKSEL is overwritten to be 128
BCLKs/LRCLK. Also, if BCLKSEL = 00, and LRCLK is 192fs or 1152fs, the generated BCLK has a
mark-space ratio of 1:2.
w
PD Rev 4.3 August 2007
23
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