W83194BR-SD 데이터 시트보기 (PDF) - Winbond

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W83194BR-SD

Winbond Clock Generator For INTEL P4 Springdale Series Chipset

Winbond 

W83194BR-SD/W83194BG-SD

CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET

5.5 Output Control Pins

PIN PIN NAME TYPE

DESCRIPTION

Deciding the reference current for the CPUCLK pairs. The pin was

connected to the precision resistor tied to ground to decide the

appropriate current. The table is show as follows.

46 IREF

IN

Board Target Trace Reference R, Iref Output Current Ioh @ Z

50 Ohms

R = 475 Iref =

2.32mA

Ioh = 6*Iref

0.7V @ 50

45

RESET#

OD

System reset signal when the watchdog is time out. This pin will

generate 250 mS when the watchdog timer is timeout.

Power good input signal comes from ACPI with high active. This

VTT_PWRGD IN 3.3V input is level sensitive strobe used to determine FS [4:0] input

are valid and is ready to sample. This pin is high active.

34

PD#*

Power Down Function. This is internal 120KΩ pull up. This is multi-

IN

function pin. When the VTT_PWRGD signal is asserted (this is,

turns from a logical Low to high), the pin will be switched into the

function of power down (PD#).

5.6 Power an GND Pins

PIN

PIN NAME

4

VDDREF

11, 17

VDDPCI

25

VDD48

28

VDD3V66

35

VDD

41

VDDCPU

48

VDDA

7, 12, 18, 24,

29, 38, 44, 47

GND

TYPE

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

DESCRIPTION

3.3V power supply for REF.

3.3V power supply for PCI.

3.3V power supply for 48 MHz.

3.3V power supply for 3V66.

3.3V power supply.

3.3V power supply for CPU.

3.3V power supply analog core.

Ground pin for 3.3 V

Publication Release Date: March, 22, 2006

-5-

Revision 1.2

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