W25P243A 데이터 시트보기 (PDF) - Winbond
부품명
상세내역
일치하는 목록
W25P243A Datasheet PDF : 18 Pages
| |||
W25P243A
AC Timing Characteristics, continued
PARAMETER
SYM. W25P243A-4A
MIN. MAX.
ADSP Setup Time
TADSS 2.0
-
ADSP Hold Time
TADSH 1.0
-
ADSC Setup Time
TADCS 2.0
-
ADSC Hold Time
TADCH 1.0
-
CE1, CE2, CE3 Setup Time
TCES
2.0
-
CE1, CE2, CE3 Hold Time
TCEH
1.0
-
GW , BWE , BWEx Setup
Time
TWS
2.0
-
GW , BWE , BWEx Hold Time TWH
1.0
-
Clock Cycle Time
TCYC
10
-
Clock High Pulse Width
TKH
4
-
Clock Low Pulse Width
TKL
4
-
Clock Access Time
TKQ
-
4.5
Clock High to Output High-Z
TKHZ
1.5
10
Clock High to Output Low-Z
TKLZ
0
-
Output Hold from Clock High TKX
1.5
-
Output Enable to Output Valid TOE
-
4.5
Output Disable to Output High-Z TOHZ
-
4.5
Output Enable to Output Low-Z TOLZ
0
-
ZZ Standby Time
TZZS
-
100
ZZ Recover Time
TZZR
100
-
W25P243A-5
MIN. MAX.
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
12
-
5
-
5
-
-
5
1.5 12
0
-
1.5
-
-
5
-
5
0
-
-
100
100
-
W25P243A-6
MIN. MAX.
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
2.0
-
1.0
-
13.3
-
6
-
6
-
-
6
1.5
13.3
0
1
1.5
-
-
6
-
6
0
-
-
100
100
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
NOTE
1
1
1
1
1
2
3
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. ADSC and ADSP should not be accessed for at least 100 nS after chip leaves ZZ mode.
4. Configuration signals LBO and FT are static and should not be changed during operation.
Publication Release Date: August 1999
-9-
Revision A3
Share Link: 