W25P243A 데이터 시트보기 (PDF) - Winbond

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W25P243A

64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

Winbond 

W25P243A

FUNCTIONAL DESCRIPTION

The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal

computers. It supports two burst address sequences for Intel™ systems (Interleaved mode) and linear

mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC

and the burst counter is incremented whenever ADV is sampled low.

BURST ADDRESS SEQUENCE

External Start Address

Second Address

Third Address

Fourth Address

INTEL SYSTEM ( LBO = VDD)

A[1:0] A[1:0] A[1:0] A[1:0]

00

01

10

11

01

00

11

10

10

11

00

01

11

10

01

00

LINEAR MODE ( LBO = VSS)

A[1:0] A[1:0] A[1:0] A[1:0]

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

The device supports several types of write mode operations. BWE and BW [8:1] support individual

byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is

used to override the byte enable signals and allows the cache controller to write all bytes to the

SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the

Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the

SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM

latches both data and valid byte enable signals from the processor.

TRUTH TABLE

CYCLE

Unselected

Unselected

Unselected

Unselected

Unselected

Begin Read

Begin Read

Continue Read

Continue Read

Continue Read

Continue Read

Suspend Read

Suspend Read

Suspend Read

Suspend Read

ADDRESS

USED

No

No

No

No

No

External

External

Next

Next

Next

Next

Current

Current

Current

Current

CE1

1

0

0

0

0

0

0

X

X

1

1

X

X

1

1

CE2 CE3 ADSP ADSC ADV

X

X

X

0

X

X

1

0

X

X

0

X

0

X

X

X

1

1

0

X

0

X

1

0

X

1

0

0

X

X

1

0

1

0

X

X

X

1

1

0

X

X

1

1

0

X

X

X

1

0

X

X

X

1

0

X

X

1

1

1

X

X

1

1

1

X

X

X

1

1

X

X

X

1

1

OE DATA WRITE*

X

Hi-Z

X

X

Hi-Z

X

X

Hi-Z

X

X

Hi-Z

X

X

Hi-Z

X

X

Hi-Z

X

X

Hi-Z

Read

1

Hi-Z

Read

0

D-Out Read

1

Hi-Z

Read

0

D-Out Read

1

Hi-Z

Read

0

D-Out Read

1

Hi-Z

Read

0

D-Out Read

-4-

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