V62C1161024L 데이터 시트보기 (PDF) - Mosel Vitelic Corporation

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V62C1161024L

Ultra Low Power 64K x 16 CMOS SRAM

Mosel Vitelic Corporation  

V62C1161024L(L)

Timing Waveform of Read Cycle 1 (Address Controlled)

Address

Data Out

tOH

Previous Data Valid

tRC

tAA

Timing Waveform of Read Cycle 2

tRC

Address

CE

(BLE/BHE)

OE

tAA

tACE

tLZ(4,5)

tBA

tBLZ(4,5)

tOE

Data Out

High-Z

tOLZ

Data Valid

tHZ(3,4,5)

tBHZ(3,4,5)

tOHZ

tOH

Data Valid

Notes (Read Cycle)

1. WE are high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.

4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to

device.

5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.

6. Device is continuously selected with CE = VIL.

7. Address valid prior to coincident with CE transition Low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write

cycle.

9. For test conditions, see AC Test Condition, Figure A.

5

REV. 1.1 April 2001 V62C1161024L(L)

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