VP603 데이터 시트보기 (PDF) - SANYO -> Panasonic
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VP603 Datasheet PDF : 8 Pages
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VP603
The θj-c(Tri) for each chip is:
θj-c (Tr1) = 45°C/W/θj-c (Tr2) to (Tr4) = 35°C/W................................ (2)
Although the loss for each transistor in a Video Pack varies with frequency and is not uniform, if we assume that the
maximum operating frequency, f = 70 MHz (clock), then the chips with the largest loss will be transistors 3 and 4 and
that loss will be about 1/4 of the total loss.Thus from the Pd for a single channel we have:
Pc (Tr3) f = 70 MHz = Pd (1CH) f = 70 MHz × 0.25 [W] ..................... (3)
Here, we must select a heat sink with a capacity θh such that the Tj of these transistors does not exceed 150°C. Equation
(4) below gives the relationship between θh and ∆Tc.
∆Tc = Pd (TOTAL) × θh ........................................................................ (4)
The required θh is calculated using this equation and equation (1).
VP603 Thermal Design Example
Conditions: Using an fH = 70 kHz class monitor, fv = 100 MHz (clock)
VCC = 80 V, VBB = 10 V, VOUT = 50 Vp-p (CL = 10 pF)
Since this class of monitor can be operated up to Ta = 60°C, here we consider the case where the maximum clock
frequency is 100 MHz.
As mentioned previously, the chip with the largest loss is transistor Tr3/Tr4. Determining the value gives:
Pc (Tr3) = 4.3 × 0.25 = 1.1 [W] .............................................................. (5)
We determine ∆Tj by substituting the value for θj-c in equation (5).
∆Tj = 1.1 × 35 = 38.5 [°C] ...................................................................... (6)
Here, Tc(max) (measured at the package surface) is taken to be under 100°C. This means that it suffices to design the
heat sink taking Tc(max) < 100°C as the design target to fulfill the conditions that Tj(max) < 150°C and furthermore that
Tc(max) < 100°C;
θh = ∆Tc ÷ Pd (TOTAL) = (Tc – Ta) ÷ [Pd (1CH) × 3]
= 40 ÷ (4.3 × 3) = 3.1°C/W
No. 5542-5/8
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