AD7710 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

일치하는 목록

AD7710

Signal Conditioning ADC

Analog Devices 

AD7710

Pin Mnemonic Function

19 TFS

20 RFS

21 DRDY

Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data

expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after

TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written

to the part.

Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the

self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the external

clocking mode, the SDATA line becomes active after RFS goes low.

Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin

will return high upon completion of transmission of a full output word. DRDY is also used to indicate when

the AD7710 has completed its on-chip calibration sequence.

22 SDATA

Serial Data. Input/output with serial data being written to either the control register or the calibration regis-

ters, and serial data being accessed from the control register, calibration registers, or the data register.

During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low).

During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The

output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.

23 DVDD

24 DGND

Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.

Ground Reference Point for Digital Circuitry.

Terminology Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero scale (not to be con-

fused with bipolar zero), a point 0.5 LSB below the first code

transition (000 . . . 000 to 000 . . . 001) and full scale, a point

0.5 LSB above the last code transition (111 . . . 110 to 111 . . .

111). The error is expressed as a percentage of full scale.

Positive Full-Scale Error

Positive full-scale error is the deviation of the last code transi-

tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage

(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar

and bipolar analog input ranges.

Unipolar Offset Error

Unipolar offset error is the deviation of the first code transition

from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-

ating in the unipolar mode.

Bipolar Zero Error

This is the deviation of the midscale transition (0111 . . . 111 to

1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)

when operating in the bipolar mode.

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal

AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat-

ing in the bipolar mode.

Positive Full-Scale Overrange

Positive full-scale overrange is the amount of overhead available

to handle input voltages on AIN(+) input greater than AIN(–) +

VREF/GAIN (for example, noise peaks or excess voltages due to

system gain errors in system calibration routines) without intro-

ducing errors due to overloading the analog modulator or to

overflowing the digital filter.

Negative Full-Scale Overrange

This is the amount of overhead available to handle voltages on

AIN(+) below AIN(–) –VREF/GAIN without overloading the

analog modulator or overflowing the digital filter. Note that the

analog input will accept negative voltage peaks even in the uni-

polar mode provided that AIN(+) is greater than AIN(–) and

greater than VSS – 30 mV.

Offset Calibration Range

In the system calibration modes, the AD7710 calibrates its offset

with respect to the analog input. The offset calibration range

specification defines the range of voltages that the AD7710 can

accept and still calibrate offset accurately.

Full-Scale Calibration Range

This is the range of voltages that the AD7710 can accept in the

system calibration mode and still calibrate full scale correctly.

Input Span

In system calibration schemes, two voltages applied in sequence

to the AD7710’s analog input define the analog input range.

The input span specification defines the minimum and maxi-

mum input voltages from zero- to full-scale that the AD7710 can

accept and still calibrate gain accurately.

–8–

REV. G

Share Link: