AD7710 데이터 시트보기 (PDF) - Analog Devices
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AD7710 Datasheet PDF : 32 Pages
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AD7710
Parameter
Limit at TMIN, TMAX
(A, S Versions)
Unit
Conditions/Comments
External Clocking Mode
fSCLK
t20
t21
t22
t23
t247
t257
t26
t27
t28
t298
t30
t318
t32
t33
t34
t35
t36
fCLK IN/5
0
0
2 × tCLK IN
0
4 × tCLK IN
10
2 × tCLK IN + 20
2 × tCLK IN
2 × tCLK IN
tCLK IN + 10
10
tCLK IN + 10
10
5 × tCLK IN/2 + 50
0
0
4 × tCLK IN
2 × tCLK IN – SCLK High
30
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Serial Clock Input Frequency
DRDY to RFS Setup Time
DRDY to RFS Hold Time
A0 to RFS Setup Time
A0 to RFS Hold Time
Data Access Time (RFS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Falling Edge to DRDY High
SCLK to Data Valid Hold Time
RFS/TFS to SCLK Falling Edge Hold Time
RFS to Data Valid Hold Time
A0 to TFS Setup Time
A0 to TFS Hold Time
SCLK Falling Edge to TFS Hold Time
Data Valid to SCLK Setup Time
Data Valid to SCLK Hold Time
NOTES
8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO OUTPUT
PIN
100pF
+2.1V
200A
Figure 1. Load Circuit for Access Time and
Bus Relinquish Time
PIN CONFIGURATION
DIP AND SOIC
SCLK 1
24 DGND
MCLK IN 2
MCLK OUT 3
23 DVDD
22 SDATA
A0 4
SYNC 5
21 DRDY
AD7710 20 RFS
MODE 6
19 TFS
TOP VIEW
AIN1(+) 7 (Not to Scale) 18 AGND
AIN1(–) 8
17 IOUT
AIN2(+) 9
16 REF OUT
AIN2(–) 10
15 REF IN(+)
VSS 11
AVDD 12
14 REF IN(–)
13 VBIAS
–6–
REV. G
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