IDT72605(2013) 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT72605
(Rev.:2013)

CMOS SyncBiFIFO 256 x 18 x 2 512 x 18 x 2

Integrated Device Technology 

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

CLKB

R/WB

ENB

tFF

FFBA

tCS

tCH

tFF

BYPB

DB0-DB17

CLKA

A0, A1, A2

tSKEW1

tCS

tDS

DATA INPUT

tSKEW1

A2, A1, A0 = 001

CSA

INDUSTRIAL TEMPERATURE RANGE

tFF

BYPASS FLAG

tFF

FIFO FLAG

tSKEW1

tCS

tSKEW1

tCS

R/WA

ENA

EFBA

tEF

FIFO FLAG

DA0-DA17

OEA

tEF

BYPASS FLAG

tOLZ

tCS

tEF

tA

tOE

tEF

FIFO FLAG

DATA OUTPUT

tOHZ

2704 drw 14

NOTES:

1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA going LOW-to-HIGH.

2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags.

3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO

mode.

Figure 11. B→A Bypass Timing

14

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