5962R9662101TCC 데이터 시트보기 (PDF) - Intersil

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5962R9662101TCC

CMOS Quad 2-Input NAND Gate

Intersil 

Schematic and Logic Diagram

CD4011BT

p

14 VDD

1†

n

(8, 6, 13)

p

2†

n

(9, 5, 12)

n

VDD

p

p

p

3 (10, 4, 11)

n

n

7 VSS

† ALL INPUTS ARE PROTECTED

VSS

BY CMOS PROTECTION NETWORK

1(8, 6,13)

2(9, 5, 12)

1 OF 4 GATES (NUMBERS

IN PARENTHESES ARE

TERMINAL NUMBERS FOR

OTHER GATES)

3

(10, 4, 11)

LOGIC DIAGRAM

2

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