24C16 데이터 시트보기 (PDF) - Turbo IC Inc

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24C16

CMOS I²C 2-WIRE BUS 16K ELECTRICALLY ERASABLE PROGRAMMABLE ROM 2K X 8 BIT EEPROM

Turbo IC Inc 

Turbo IC, Inc.

24C16

DEVICE ADDRESSING:

Following the start condition, the master will issue a device

address byte consisting of 1010 (B10) (B9) (B8) (R/W) to

access the selected Turbo IC 24C16 for a read or write op-

eration. The B[10:8] bits are the 3 most significant bits of the

memory address. The (R/W) bit is a high (1) for read and low

(0) for write.

DATA INPUT DURING WRITE OPERATION:

During the write operation, the Turbo IC 24C16 latches the

SDA bus signal on the rising edge of the SCL clock.

DATA OUTPUT DURING READ OPERATION:

During the read operation, the Turbo IC 24C16 serially shifts

the data onto the SDA bus on the falling edge of the SCL

clock.

MEMORY ADDRESSING:

The memory address is sent by the master in the form of 2

bytes. Memory address bits B[10:8], are included in the de-

vice address byte.The remaining memory address bits B[7:0]

are included in the second byte. The memory address byte

can only be sent as part of a write operation.

BYTE WRITE OPERATION:

The master initiates the byte write operation by issuing a

start condition, followed by the device address byte 1010

(B10) (B9) (B8) 0, followed by the memory address byte,

followed by one data byte, followed by an acknowledge, then

a stop condition. After each byte transfer, the Turbo IC 24C16

acknowledges the successful data transmission by pulling

the SDA bus low. The stop condition starts the internal

EEPROM write cycle, and all inputs are disabled until the

completion of the write cycle. If the WP pin is high (1) and the

memory address is within the upper half (400-7FFH) of

memory, then the stop condition does not start the internal

write cycle and the Turbo IC 24C16 is immediately ready for

the next command.

upper half (400-7FFH) of memory, then the stop condition

does not start the internal write cycle, and the Turbo IC 24C16

is immediately ready for the next command.

POLLING ACKNOWLEDGE:

During the internal write cycle of a write operation in the Turbo

IC 24C16, the completion of the write cycle can be detected

by polling acknowledge.The master starts acknowledge poll-

ing by issuing a start condition, then followed by the device

address byte 1010 (B10) (B9) (B8) 0. If the internal write

cycle is finished, the Turbo IC 24C16 acknowledges by pull-

ing the SDA bus low. If the internal write cycle is still ongoing,

the Turbo IC 24C16 does not acknowledge because it’s in-

puts are disabled. Therefore, the device will not respond to

any command. By using polling acknowledge, the system

delay for write operations can be reduced. Otherwise, the

system needs to wait for the maximum internal write cycle

time, tWC, given in the spec.

POWER ON RESET:

The Turbo IC 24C16 has a Power On Reset circuit (POR) to

prevent data corruption and accidental write operations dur-

ing power up. On power up, the internal reset signal is on

and the Turbo IC 24C16 will not respond to any command

until the VCC voltage has reached the POR threshold value.

PAGE WRITE OPERATION:

The master initiates the page write operation by issuing a

start condition, followed by the device address byte 1010

(B10) (B9) (B8) 0, followed by the memory address byte,

followed by up to 16 data bytes, followed by an acknowledge,

then a stop condition. After each byte transfer, the Turbo IC

24C16 acknowledges the successful data transmission by

pulling SDA low. After each data byte transfer, the memory

address counter is automatically incremented by one. The

stop condition starts the internal EEPROM write cycle only if

the stop condition occurs in the clock cycle immediately fol-

lowing the acknowledge (10th clock cycle). All inputs are dis-

abled until the completion of the write cycle. If the WP pin is

high (1) and the memory address is within the

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