LH6V4256K-10 데이터 시트보기 (PDF) - Sharp Electronics
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LH6V4256K-10 Datasheet PDF : 18 Pages
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CMOS 1M (256K × 4) Dynamic RAM
LH6V4256
AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4 (TA = 0 to +70°C, VCC = 3.3 V ±0.3 V)
READ CYCLE
PARAMETER
SYMBOL MIN. MAX.
Random read or write cycle time
tRC
190
Access time from RAS
tRAC
100
Access time from column address
tAA
50
Access time from CAS
tCAC
40
Access time from OE
tOEA
35
Row address setup time
tASR
0
Row address hold time
tRAH
15
Column address setup time
tASC
0
Column address hold time (RAS)
tCAH
20
Column address delay time (RAS)
tRAD
20
50
Column address lead time (RAS)
tRAL
50
RAS pulse width
tRAS
100 10,000
RAS precharge time
tRP
80
CAS precharge time (RAS ↓)
tCRP
0
CAS delay time (RAS)
tRCD
25
60
CAS lead time (RAS)
tRSL
30
CAS pulse width
tCAS
40 10,000
CAS hold time
tCSH
100
OE lead time (RAS)
tROL
0
Output data disable time (CAS)
tOFF
30
Output data disable time (OE)
tOEZ
30
Output data hold time (CAS)
tSOH
0
Output data hold time (OE)
tOOH
0
Read command setup time (CAS)
tRCS
0
Read command hold time (CAS)
tRCH
10
Read command hold time (RAS ↑)
tRRHP
10
Read command hold time (RAS ↓)
tRRHN
115
Transition time (rise and fall)
tT
3
35
Refresh time interval
tREF
8
NOTES:
1. For proper memory function, at least 200 µs of pause time should
be kept after power on, followed by several dummy cycles. When
RAS = VIH is continued for more than 8 ms, the same dummy cycles
should be given. Usually eight ordinary refresh cycles should be
given.
2. The required VCC current (ICC) during power on depends on the input
levels of RAS. If RAS = VIL during power on, the device goes into
an active cycle, and ICC exhibits large current transients. It is rec-
ommended that RAS tracks with VCC or be held at a valid VIH during
power on.
3. AC characteristics assume tT = 5 ns.
4. AC characteristics assume the following condition (see figure at
right).
5. Load condition for 1TTL + 30 pF.
6. tRAD (MAX) is the maximum point for tRAD where tRAC (MAX) is
ensured, and does not represent a limit of operation. If tRAD ≥ tRAD
(MAX), the access time comes under the control of tAA.
7. tRCD (MAX) is the maximum point for tRCD, where tRAC (MAX) is
ensured and does not represent a limit of operation. If tRCD ≥ tRCD
(MAX), the access time comes under the control of tCAC.
8. The operation is ensured when either tRRHN, tRRHP, or tRCH is satisfied.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
NOTE
5
5
5
5
6
7
8
8
8
INPUT
LEVEL
OUTPUT
JUDGMENT
LEVEL
2.3 V
0.6 V
2.15 V
0.4 V
6V4256-6
2-19
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