LH6V4256K-10 데이터 시트보기 (PDF) - Sharp Electronics

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LH6V4256K-10

CMOS 1M(256K x 4) dynamic RAM

Sharp Electronics 

LH6V4256

FUNCTION

• 262,144 words × 4 bit

• Access time: 100 ns (MAX)

• Cycle time: 190 ns (MIN)

• Fast page mode cycle time: 60 ns (MIN)

• Power supply: +3.3 V ±0.3 V

• Power consumption (MAX):

Operating: 126 mW

Standby: 0.54 mW

• Built-in latch circuit for row-address,

column-address, and input data

• OE = Don’t care in early write operation

• RAS only refresh, hidden refresh, and

CAS before RAS refresh capability

• On-chip refresh counter

• 512 refresh cycle/8 ms

• Packages:

20-pin, 300-mil DIP

26-pin, 300-mil SOJ

28-pin, 8 × 13 mm2 TSOP (Type I)

CMOS 1M (256K × 4) Dynamic RAM

DESCRIPTION

The LH6V4256 is a 262,144 word × 4-bit dynamic

RAM which allows fast page mode access. The

LH6V4256 is fabricated on SHARP’s advanced CMOS

double-level polysilicon gate technology. With its input

multiplexed and packaged in the standard 20-pin DIP,

26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to

realize memory systemswith low power dissipation and

large memory capacity. The LH6V4256 operates on a

single +3.3 V power supply and the built-in biasing

voltage generator circuit.

PIN CONNECTIONS

20-PIN DIP

TOP VIEW

I/O1 1

I/O2 2

WE 3

RAS 4

NC 5

A0 6

A1 7

A2 8

A3 9

VCC 10

20 VSS

19 I/O 4

18 I/O3

17 CAS

16 OE

15 A8

14 A7

13 A6

12 A5

11 A4

6V4256-1

Figure 1. Pin Connections for DIP Package

2-14

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