TDA9951 데이터 시트보기 (PDF) - Philips Electronics
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TDA9951 Datasheet PDF : 41 Pages
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NXP Semiconductors
TDA9951
CEC/I2C-bus translator
Table 3. Pin description …continued
Symbol
Pin Type[1] Description
VFD_STR 13 O
VFD strobe line. Pulsed HIGH latches clocked output at the VFD
driver
VFD_BLK 14 O
VFD blank line. Default HIGH blanks output at the VFD display
driver. The polarity is configurable using the I2C-bus
KCOL
15 O
key matrix column output[2]
PSEN
16 I
power sense input detects power supply type.
LOW-level = battery
HIGH-level = main power
RSVD0
17 I
reserved pin; connect to ground
RSVD1
18 O
reserved pin
KROW4
19 I
key matrix row input[2]
KROW3
20 I
key matrix row input[2]
VDD
KROW2
21 P
22 I
power supply voltage
key matrix row input[2]
KROW1
23 I
key matrix row input[2]
KROW0
24 I
key matrix row input[2]
RSVD2
25 O
reserved pin
A0
26 I
I2C-bus slave address bit. This pin configures the least
significant bit A0 of the I2C-bus slave address; connect to:
IR_VAL
27 O
VDD (HIGH) sets A0 to logic 1 (address 35h)
VSS (LOW) sets A0 to logic 0 (address 34h)
pulse LOW for 65 ms after every valid IR frame is received, to
indicate activity using an LED
IR_DAT
28 I
input from external infrared demodulator.
LOW-level = active IR pulse,
HIGH-level = no IR pulse (a space)
[1] P = power supply, I = input, O = output and I/O = Input and Output.
[2] See Figure 15 “Application diagram” on page 35.
8. Functional description
The TDA9951 controls the interface between the CEC-line and the I2C-bus using its
internal processor and embedded software.
8.1 Device addressing
The SDA and SCL pins are managed by the I2C-bus peripheral which automatically
communicates in Standard mode (100 kbit/s) or Fast mode (400 kbit/s) as an I2C-bus
slave.
The TDA9951 signals the host processor that data is ready by asserting the INT output.
The polarity is configurable using the INT_POL bit in the CCONR register (see Table 14).
TDA9951_1
Product data sheet
Rev. 01 — 7 August 2008
© NXP B.V. 2008. All rights reserved.
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