TB62707FG 데이터 시트보기 (PDF) - Toshiba

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TB62707FG

TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Toshiba 

PIN CONNECTION (Top view)

TB62707FG

BLOCK DIAGRAM

TIMING DIAGRAM

Note:

Latches are level sensitive, not rising edge sensitive and not synchronous CLOCK.

Input of LATCH −terminal to "H" level, data passes latches, and input to "L" level, data hold latches.

Input of ENABLE −terminal to "H" level, all output (OUT0~7) do off.

2

2006-06-14

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