STV5346 데이터 시트보기 (PDF) - STMicroelectronics
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STV5346 Datasheet PDF : 21 Pages
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STV5346 - STV5346/H - STV5346/T
FUNCTIONAL DESCRIPTION (continued)
III - I2C Bus Register Map (see Table 2)
Registers R0 to R10 are write only whilst R11A is a
read/write and R11B is a read only register respect
to the microprocessor.
The automatic succession on a byte basis is indi-
cated by the arrows in Table 2.
In the normal operating mode TB should be set to
logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R11A are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimal value 20H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07H.
Table 2 : Register specification
D7
D6
D5
X24
FREE
(1)
POSITION RUNNING
PLL
(1)
7 + P/
ACQ.
8 BIT
ON/OFF
(1)
BANK
ACQ.
SELECT CCT
A2
A1
(1)
(1 )
(1)
D4
D3
DISABLE (1)
ROLLING
HEADER
GHOST
ROW
ENABLE
DEW/
FULL
FIELD
ACQ.
TB
CCT
A0
PRD4
PRD3
D2
D1
D0
EVEN
(1)
SEL 11B
OFF
↵
TCS
T1
T0
ON
↵
START START START
COLUMN COLUMN COLUMN
SC2
SC1
SC0
↵
PRD2
PRD1
PRD0
(1)
BKGND
OUT
BKGND
OUT
(1 )
BKGND
IN
BKGND
IN
(1)
COR
OUT
COR
OUT
STATUS
ROW
BTM/TOP
(1)
CURSOR
ON/OFF
(1 )
CONCEAL/
REVEAL
(1)
(1)
(1)
D7
(R/W)
60Hz
(1 )
(1 )
D6
( R/W)
0
(1)
C5
D5
(R/W)
0
(1)
COR
(1)
TEXT
A2
TEXT
A1
PON
A0
PON
↵
IN
OUT
IN
OUT
IN
↵
COR
TEXT
TEXT
PON
PON
IN
TOP/
OUT
IN
OUT
IN
↵
SINGLE/ BOX ON BOX ON BOX ON
BOTTOM DOUBLE 24
1-23
0
HEIGHT
(1)
R4
C4
D4
(R/W)
CLEAR A2
MEM.
A1
A0
↵
R3
R2
R1
R0
↵
C3
D3
C2
D2
C1
D1
C0
D0
↵
(R/W)
(R/W)
(R/W)
(R/W)
0
0
0
0
VCS
QUAL
(1) Reserved register bits : must be set to 0
R0 Mode 0
R1 Mode 1
R2 Page request address
R3 Page request data
R4 Display chapter
R5 Display control (normal)
R6
Display control
(newsflash / subtitle)
R7 Display mode
R8 Active chapter
R9 Active row
R10 Active column
R11A Active data
R11B Status
10/21
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