STV5346 데이터 시트보기 (PDF) - STMicroelectronics

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STV5346

MONOCHIP TELETEXT DECODER WITH 8 INTEGRATED PAGES

STMicroelectronics 

STV5346 - STV5346/H - STV5346/T

Figure 3 : Master Synchronization Mode - Hardware Configuration

1

Synchro

Extractor

Line PLL

Line PLL

MA/SL

2

+5V

4

POL

VCS

R1D2 = ”0”

TCS

R1D2 = ”1”

Bit R1D2

I2C

Control

STTV

Output signal on STTV Pin :

POL grounded

VCS when R1D2 = 0

TCS when R1D2 = 1

POL to VDD

VCS when R1D2 = 0

TCS when R1D2 = 1

Figure 4 : Master Synchronization Mode - Delivered Composite Synchronization Signal

VCS, TCS

(interlaced)

621 622 623 624 625

1

2

(308) (309) (310) (311) (312)

3

4

5

6

VCS, TCS

(interlaced)

309 310 311 312 313 314

(1)

315 316 317 318 319

(2)

(3)

(4)

(5) (6)

TCS

(non-interlaced)

308 309 310 311

The number positions indicate the end of lines.

Internal signals :

- VCS composite synchro from CVBS signal,

- TCS Teletext composite synchro.

Figure 5 : Slave Synchronization Mode

MA/SL

+5V 2

+5V

POL

4

312

1

2

LFB

5

6

FFB

SCS

3

4

5

6

POL grounded, Inputs Signals :

are LFB line flyback synchro on Pin 5

FFB field flyback synchro on Pin 6

or SCS synchro composite signal on Pins 5 and 6

POL to VDD, Inputs Signals :

are LFB line flyback synchro on Pin 5

FFB field flyback synchro on Pin 6

or SCS synchro composite signal on Pins 5 and 6

Note : R1D0 and R1D1 must be set to 1.

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