HSP50307EVAL1(1996) 데이터 시트보기 (PDF) - Intersil
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HSP50307EVAL1 Datasheet PDF : 8 Pages
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Pinout
HSP50307
28 LEAD SOIC
TOP VIEW
MCLK 1
TXCLK 2
TX_EN 3
TX_DATA 4
RESET 5
DGND 6
AVCC 7
AGND 8
IBBOUT 9
QBBOUT 10
QBBIN 11
IBBIN 12
DAC_REF 13
VCM_REF 14
28 CCLK
27 CDATA
26 C_EN
25 DVCC
24 RCLK
23 AGND
22 PD_OUT
21 VCO_IN
20 VCO_SET
19 AVCC
18 MOD_OUT-
17 MOD_OUT+
16 AVDD
15 AGND
Pin Description
SYMBOL TYPE
DESCRIPTION
MCLK
I Master clock input (25.6MHz). (D)
TXCLK
O PSK data clock (256kHz) for PSK_DATA_IN. (D)
TX_EN
I Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is
extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D)
TX_DATA
I 256 KBPS serial data input. (D)
RESET
I Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is
disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is de-
asserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper opera-
tion. (D)
DGND
I Negative supply for the digital filters and control. (P)
AVCC
I Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P)
AGND
I Negative supply for the quadrature modulator. AGND is tied to GND. (P)
IBBOUT
O I baseband filtered output. (A)
QBBOUT
O Q baseband filtered output. (A)
QBBIN
I Q baseband modulator input. (A)
IBBIN
I I baseband modulator input. (A)
DAC_REF
VCM_REF
O D/A reference node. A 0.1µF capacitor to ground is suggested. (A)
O Modulator common mode reference node. A 0.1µF capacitor to ground is suggested. (A)
AGND
I Negative supply for the cable interface. (P)
AVDD
I Positive supply for the cable interface (+9V analog). (P)
MOD_OUT+ O Positive output drive pin for the cable interface. (A)
MOD_OUT- O Negative output drive pin for the cable interface. (A)
7-69
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