STK12C68 데이터 시트보기 (PDF) - Cypress Semiconductor
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STK12C68 Datasheet PDF : 24 Pages
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STK12C68
Software RECALL
■ The duty cycle of chip enable
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of Read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled Read operations is
performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
■ The overall cycle rate for accesses
■ The ratio of Reads to Writes
■ CMOS versus TTL input levels
■ The operating temperature
■ The VCC level
■ I/O loading
Figure 4. Current Versus Cycle Time (Read)
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
. Internally, RECALL is a two step procedure. First, the SRAM data
nly is cleared; then, the nonvolatile information is transferred into the
o SRAM cells. After the tRECALL cycle time, the SRAM is again
s ready for Read and Write operations. The RECALL operation
am does not alter the data in the nonvolatile elements. The nonvol-
gr atile data can be recalled an unlimited number of times.
pro Data Protection
. tion The STK12C68 protects data from corruption during low voltage
ns uc conditions by inhibiting all externally initiated STORE and Write
ig od operations. The low voltage condition is detected when VCC is
es pr less than VSWITCH. If the STK12C68 is in a Write mode (both CE
D g and WE are low) at power up after a RECALL or after a STORE,
w in the Write is inhibited until a negative transition on CE or WE is
e go detected. This protects against inadvertent writes during power
N n up or brown out conditions.
d for ort o Noise Considerations
nde upp The STK12C68 is a high speed memory. It must have a high
e s frequency bypass capacitor of approximately 0.1 µF connected
mm to between VCC and VSS, using leads and traces that are as short
co tion as possible. As with all high speed CMOS ICs, careful routing of
e c power, ground, and signals reduce circuit noise.
ot R odu Hardware Protect
N pr The STK12C68 offers hardware protection against inadvertent
In STORE operation and SRAM Writes during low voltage condi-
Figure 5. Current Versus Cycle Time (Write)
tions. When VCAP<VSWITCH, all externally initiated STORE
operations and SRAM Writes are inhibited. AutoStore can be
completely disabled by tying VCC to ground and applying +5V to
VCAP. This is the AutoStore Inhibit mode; in this mode, STOREs
are only initiated by explicit request using either the software
Preventing Store
sequence or the HSB pin.
The STORE function is disabled by holding HSB high with a
Low Average Active Power
driver capable of sourcing 30 mA at a VOH of at least 2.2V,
because it must overpower the internal pull down device. This
CMOS technology provides the STK12C68 the benefit of
drawing significantly less current when it is cycled at times longer
than 50 ns. Figure 4 shows the relationship between ICC and
Read or Write cycle time. Worst case current consumption is
shown for both CMOS and TTL input levels (commercial temper-
ature range, VCC = 5.5V, 100% duty cycle on chip enable). Only
standby current is drawn when the chip is disabled. The overall
device drives HSB LOW for 20 μs at the onset of a STORE.
When the STK12C68 is connected for AutoStore operation
(system VCC connected to VCC and a 68 μF capacitor on VCAP)
and VCC crosses VSWITCH on the way down, the STK12C68
attempts to pull HSB LOW. If HSB does not actually get below
VIL, the part stops trying to pull HSB LOW and abort the STORE
attempt.
average current drawn by the STK12C68 depends on the
following items:
Document Number: 001-51027 Rev. *C
Page 6 of 24
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