ST7586S 데이터 시트보기 (PDF) - Sitronix Technology Co., Ltd.
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ST7586S Datasheet PDF : 63 Pages
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ST7586S
FUNCTION DESCRIPTION
Microprocessor Interface
Chip Select Input
CSB pin is used for chip selection. ST7586S can interface with an MPU when CSB is "L". If CSB is “H”, the inputs of A0, ERD
and RWR with any combination will be ignored and D[7:0] are high impedance. In 3-Line and 4-Line serial interfaces, the
internal shift register and serial counter are reset when CSB is “H”.
Interface Selection
The interface selection is controlled by IF[3..1] pins. Please refer to the table below:
Table 1
Setting
IF3 IF2 IF1
MPU Type
Interface Pin Function
CSB A0 RWR ERD
D[7:0]
H
H
L Parallel 8080 series MPU
/WR /RD
A0
D[7:0]
H
L
L Parallel 6800 series MPU
R/W E
CSB
L
H
H Serial 4-Line series MPU
--
-- D1=A0; D0=SDA. D[7:2] are not used.
SCL
L
H
L Serial 3-Line series MPU
--
-- D0=SDA. D[7:1] are not used.
Note: The un-used pins are marked as “--” and should be fixed to “H” by “VDD1”.
Parallel Interface
When parallel interface is selected, the interface transmission type will be determined by the combination of the control
signals. Please refer to the table below:
Table 2
8080 series MPU
/WR
/RD
6800 series MPU
R/W
E
A0
CSB
Interface Transmission Type
↑
H
L
↓
L
Write Command
↑
H
L
↓
H
Write Display Data or Parameter
L
H
↓
H
↑
H
Read Display Data or Parameter Start
H
↑
H
↓
H
Read Display Data or Parameter Stop
Note: Reading Display Data or Parameter is specified by the instruction before the read operation.
Serial Interface
In serial interface mode (4-Line or 3-Line), IC is active when CSB is “L”. Control signals (SDA, SCL and A0 for 4-Line) are
enabled when CSB is “L”. When CSB is “H”, the MPU interface is not active and the internal shift register and counter are
reset. It is recommended to set CSB to “H” after each byte transmission.
In 4-Line serial interface, A0 signal is latched at the 8th rising edge of the SCL signal (refer to Fig. 1).
Ver-1.1a
Fig. 1
Write-Operation of 4-Line Serial Interface
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2009/11/30
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