ST7033 데이터 시트보기 (PDF) - Sitronix Technology Co., Ltd.
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ST7033 Datasheet PDF : 39 Pages
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ST7033
Read/Write operation control pin (if using Parallel interface).
MPU Type E_RD
Interface Mode
Signals (Instruction or Data) on
data bus will be latched by MPU
6800-series
E
E_RD
I
or this IC (depends on R/W) at
1
the falling edge of this signal.
Internal status (or display data)
8080-series /RD will be read out to data bus after
the falling edge of this signal.
Data Bus. If /CSB signal is not actived, D7…D0 are high impedance.
Parallel interface (6800 or 8080):
I/O port which is connected to the standard 8-bit MPU data bus.
D0…D7
I
Serial SPI interface (3 line or 4 line):
8
SCLK: D0;
SDA: D1~D3;
D4~D7 must connect to VDD1.
LCD DRIVER SUPPLY
OSC=”H”: Use the built-in oscillator.
OSC=”L”: Both external clock and built-in oscillator are inhibited. And
OSC
the display circuits will not be clocked and kept in a DC state. To
I
1
avoid this, the chip should always be put into Power-Down Mode
before stopping the clock.
If using external clock, connect this pin to the external clock.
POWER SUPPLY
VSS
Power Ground.
5
Digital circuits supply voltage.
VDD1
Power The 2 power supply rails, VDD1 and VDD2, could be connected together.
4
Use this power to be the high voltage level for the Option pins.
Analog circuits supply voltage.
VDD2
Power
4
The 2 power supply rails, VDD and VDD2, could be connected together.
Negative LCD driver supply voltages.
XV0I, XV0O, XV0S Power XV0I, XV0O & XV0S should be separated in ITO layout.
7
Supply XV0I, XV0O & XV0S should be connected together in FPC layout.
This is a multi-level power supply for the liquid crystal.
V0 ≥ VG ≥ VM ≥ VSS ≥ XV0
V0I, V0O, V0S;
Power V0I, V0O & V0S should be separated in ITO layout.
VGI, VGO, VGS Supply V0I, V0O & V0S should be connected together in FPC layout.
6
VGI, VGO & VGS should be separated in ITO layout.
VGI, VGO & VGS should be connected together in FPC layout.
Power
VM
Supply LCD driving voltage for commons.
3
VRS
Reserved to monitor internal Voltage Regulator reference level, must be left
Power
1
open.
Configuration Pins
Test pin.
MODE
I
1
Must fix to “L”
Set Booster stage.
CP
I
VSS=4X;
1
VDD=5X.
Ver 1.1
8/39
2009/07/17
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