ST7033 데이터 시트보기 (PDF) - Sitronix Technology Co., Ltd.
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ST7033 Datasheet PDF : 39 Pages
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ST7033
6. PINNING DESCRIPTIONS
Pin Name
I/O
LCD driver outputs
SEG0 to SEG95
O
COM0 to COM3
O
Description
Pin Count
LCD segment driver outputs.
The display data and the M signal control the output voltage of segment
driver.
Segment drover output voltage
Display data
Frame
Normal display Reverse display
96
H
-
VG
VSS
H
+
VSS
VG
L
-
VSS
VG
L
+
VG
VSS
Power save mode
VSS
VSS
LCD column driver outputs.
The internal scanning data and the M signal control the output voltage of
common driver.
Display data
Frame
Common drover output voltage
Normal display Reverse display
68
H
-
XV0
H
+
V0
L
-
VM
L
+
VM
Power save mode
VSS
MICROPROCESSOR INTERFACE
Microprocessor interface mode selection pins.
PS1
PS0
Interface Mode
1
1
8080-series parallel MPU interface
PS[1,0]
I
2
1
0
6800-series parallel MPU interface
0
1
4-line SPI MPU interface
0
0
3-line SPI MPU interface
/CSB
Chip select input pin.
I
Data/instruction I/O is enabled only when /CSB is "L". When chip select is
1
non-active, D7…D0 are high impedance.
Reset input pin.
/RESB
I
1
When /RESB is "L", initialization is executed.
It determines whether the data bits are data or a command.
A0
I
A0=" H “: Indicates that D0 to D7 are display data.
A0=" L “: Indicates that D0 to D7 are control data.
1
There is no A0 pin in three line , so this pin can fix to ” H”
Read/Write operation control pin (if using Parallel interface).
MPU Type RW_WR
Interface Mode
R/W=”H”: Read;
6800-series R/W
RW_WR
I
R/W=”L”: Write.
1
Signals (Instruction or Data) on
8080-series /WR data bus will be latched at the
raising edge of this signal.
Ver 1.1
7/39
2009/07/17
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