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SST34HF1681

16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory

Silicon Storage Technology 

16 Mbit Concurrent SuperFlash + 8 Mbit SRAM ComboMemory

SST34HF1681

Advance Specifications

TOP VIEW (balls facing down)

8

A15 NC NC A16 NC VSS

7

A11 A12 A13 A14 NC DQ15 DQ7 DQ14

6

A8 A19 A9 A10 DQ6 DQ13 DQ12 DQ5

5

WE# BES2 NC

DQ4 VDDS NC

4

WP# RST# RY/BY#

DQ3 VDDF DQ11

3

LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2

2

A7 A6 A5 A4 VSS OE# DQ0 DQ8

1

A3 A2 A1 A0 BEF# BES1#

ABCDEFGH

SST34HF1681

561 ILL F03.0

FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (8MM X 10MM) COMBOMEMORY PINOUT

TABLE 2: PIN DESCRIPTION

Symbol Pin Name

Functions

AMS1 to A0 Address Inputs

DQ15-DQ0 Data Inputs/Outputs

To provide flash address, A19-A0.

To provide SRAM address, A18-A0

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a flash Erase/Program cycle. The outputs are in

tri-state when OE# is high or BES1# is high or BES2 is low and BEF# is high.

BEF#

Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low

BES1# SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low

BES2

SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high

OE#

Output Enable

To gate the data output buffers

WE#

Write Enable

To control the Write operations

UBS#

LBS#

WP#

Upper Byte Control (SRAM)

Lower Byte Control (SRAM)

Write Protect

To enable DQ15-DQ8

To enable DQ7-DQ0

To protect and unprotect sectors from Erase or Program operation

RST#

Reset

To Reset and return the device to Read mode

RY/BY# Ready/Busy#

To output the status of a Program or Erase Operation

RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required to

allow RY/BY# to transition high indicating the device is ready to read.

VSS

VDDF

VDDS

NC

Ground

Power Supply (Flash)

Power Supply (SRAM)

No Connection

2.7-3.3V Power Supply to Flash only

2.7-3.3V Power Supply to SRAM only

Unconnected pins

1. AMS = Most Significant Address

T2.1 561

©2001 Silicon Storage Technology, Inc.

7

S71214-00-000 12/01 561

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