SP8647BDG 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SP8647BDG

250MHz ÷ 10/11

Zarlink Semiconductor Inc 

SP8647

250MHz410/11

DS3643-1·2

The SP8647 is an ECL variable modulus divider, with

ECL10K and TTL/CMOS compatible outputs. It divides by 10

when either of the ECL control inputs, PE1 or PE2, is in the high

state and by 11 when both are low (or open circuit).

The two clock inputs are interchangeable and either will act

as a clock inhibit when connected to an ECL high level.

Normally, one input is left open circuit and the other is AC-

coupled, with externally applied bias.

FEATURES

s ECL Compatible Inputs/Outputs

s Open Collector TTL/CMOS Output

s AC-Coupled Input (External Bias)

QUICK REFERENCE DATA

s Supply Voltage: 25·2V60·25V (ECL), 5·0V60·25V (TTL)

s Power Consumption: 260mW

s Temperature Range: 230°C to 170°C

ABSOLUTE MAXIMUM RATINGS

Supply voltage, |VCC2VEE|

Output current

Storage temperature range

Max. junction temperature

Open collector voltage (pin 11)

Max. clock input voltage

Max. open collector current

8V

20mA

265°C to 1150°C

1175°C

112V

2·5V p-p

15mA

CLOCK INPUT 1 1

16 CLOCK INPUT 2

 PE1 2

CONTROL INPUTS 

 PE2 3

15 NC

14 NC

NC 4

13 NC

SP8647

VCC 5

12 VEE

NC 6

11 TTL/CMOS OUTPUT

NC 7

10 NC

ECL OUTPUT 8

9 ECL OUTPUT

DG16

Fig. 1 Pin connections - top view

ORDERING INFORMATION

SP8647 B DG

5962-90618 (SMD)

VCC

5

11 TTL/CMOS

OUTPUT

PE1 2

PE2 3

CLOCK INPUT 1 1

CLOCK INPUT 2 16

D1 Q1

CK

D2 Q2

CK

D3 Q3

CK

D4 Q4

CK Q4

8 OUTPUT

9

OUTPUT

12

VEE

Fig. 2 Functional diagram

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