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SC4614 데이터 시트보기 (PDF) - Semtech Corporation

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SC4614
Semtech
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SC4614 Datasheet PDF : 14 Pages
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SC4614
POWER MANAGEMENT
Applications Information (Cont.)
60
30
Fz1
0
-30
Fp1 COM PENSATOR GAI N
Fp2
Fz2
Fo
Fz
LOOP GAIN
CONV ERTER GAI N
Fc
-60
100
1K
10K
100 K
FR EQ UENCY (Hz )
Fig. 4. Bode plots for control loop design
(2). Select the open loop crossover frequency Fc located
at 10% to 20% of the switching frequency. At Fc, find the
required DC gain.
(3). Use the first compensator pole Fp1 to cancel the
ESR zero Fz.
(4). Have the second compensator pole Fp2 at half the
switching frequency to attenuate the switching ripple and
high frequency noise.
(5). Place the first compensator zero Fz1 at or below
50% of the power stage resonant frequency Fo.
(6). Place the second compensator zero Fz2 at or below
1M
the power stage resonant frequency Fo.
A MathCAD program is available upon request for the
calculation of the compensation parameters.
C2
LAYOUT GUIDELINES
C1
R2
Vc
2
1
3
VREF
0. 5V
C3
R3
Rt op
Rb ot
The switching regulator is a high di/dt power circuit. Its
Printed Circuit Board (PCB) layout is critical. A good lay-
Vo out can achieve an optimum circuit performance while
minimizing the component stress, resulting in better sys-
tem reliability. During PCB layout, the SC4614 controller,
MOSFETs, inductor, and power decoupling capacitors have
to be considered as a unit.
The following guidelines are typically recommended for
using the SC4614 controller.
Fig. 5. Compensation network
The top resistor Rtop of the voltage divider in Fig. 5 can
be chosen from 1k to 5k. Then the bottom resistor Rbot
is found from:
Rbot
=
0.5V
VO - 0.5V
× Rtop
where 0.5V is the internal reference voltage of the
SC4614.
(1). Place a 4.7uF to 10uF ceramic capacitor close to
the drain of top MOSFET for the high frequency and high
current decoupling. The loop formed by the capacitor,
the top and bottom MOSFETs must be as small as pos-
sible. Keep the input bulk capacitors close to the drain
of the top MOSFETs.
(2). Place the SC4614 over a quiet ground plane to avoid
pulsing current noise. Keep the ground return of the gate
drive short.
(3). Connect bypass capacitors as close as possible to
the decoupling pins (DRV and Vcc) to the ground pin GND.
The trace length of the decoupling capacitor on DRV pin
should be no more than 0.2” (5mm).
The other components of the compensator can be cal- (4). Locate the components of the bootstrap circuit close
culated using following design procedure:
to the SC4614.
(1). Plot the converter gain, including LC filter and PWM
modulator.
2005 Semtech Corp.
9
www.semtech.com

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