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SC1406G
Semtech Corporation
SC1406G Datasheet PDF : 28 Pages
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SC1406G
POWER MANAGEMENT
Additional Functions:
The SC1405 also provides two voltage protection functions:
1 A drive voltage under voltage lockout (UVLO) with
output on PRDY, pin 7
2 An output over voltage protection (OVP) using input
OVPS, pin 1
UVLO shuts off the drivers when Vcc is less than 4.4Vdc; in this
condition, PRDY is driven low, and may be used to disable the
SC1406G as well. OVP is implemented using a resistive divider
to a 1.20V +/- 55mV reference. In order to keep the voltage
within the 2.1V processor specification:
R14
Z. VREFMAX:= VOVPMAX⋅ R14 + R15
With R14=10kW, R15=6.65kW. Solving this equation for the
minimum trip voltage yields VOVPMIN=1.906V. Since this is only
~250mV from the zero load voltage, a noise filter capacitor
(C14) is required, and should be chosen that the R14||C15
time constant is longer than the minimum switching period. The
OVP input has very fast response, so C14 needs to be located
directly at the pin, and the length of the OVP trace should be
minimized.. Ground pin 1 to disable OVP.
A logic output signal DPSPDR (pin11) mirrors BG when SMOD is
HI; it is HI when SMOD is LO.
Additional notes:
Since the SC1405 puts out large, sharp pulses, decoupling and
grounding are very important. The Vcc decoupling capacitor,
C16 should be at least 1uF ceramic, and located right at the
chip with the + terminal connected directly to Vcc (pin 8) and
the terminal connected directly to PGND (pin 10). Note that
the SC1405 connects to both the power and analog grounds.
Grounding is described in the following section.
LAYOUT GUIDELINES:
As with any high-speed switching converter, the area of high
current loops needs to be minimized. The two major loops are
(referring to Figure 2):
In addition:
1. Separate the noisy and quiet areas of the circuit.
A significant benefit of the controller/driver
architecture is that the control circuit does not
have to coexist in an environment of thousands of
volts and amps per microsecond.
2. Place the SC1405 so as to reduce the trace
length to the synchronous rectifier(s).
3. Place the current-sense resistor as close as
possible to the output capacitors; inductance
from the voltage sense point to ground results in
extra output ripple.
4. Connections and routing of the differential pairs
are critical. The first three items are essential; the
others are suggested for additional guidance.
a. Run the traces as close together as
possible.
b. Use minimum width traces to reduce
capacitive coupling.
c. Run a single pair as far as possible; split
them at the resistors as close as
possible to the SC1406; put the filter
capacitors as close as possible to the
device.
d. In noisy environments, use a guard ring
(ground trace around the differential
pair). Tie the ring to ground every 2-4
cm.
e. Run the traces in a quiet layer; use the
minimum number of vias.
5. Minimize the area of the switching node and any
other high-speed nodes.
6. Layout the protection circuitry (OVP, LBIN) keeping
noise in mind:
a. Minimize the length and area of traces
to the pins.
b. Put the noise filter capacitor next to the
pin.
1. From the input capacitors, through Q3, L1, and
C19 C24, returning through PGND;
2. From Q4/Q5 through L1 and C19 C24, returning
through PGND.
Secondary loops are in the gate drive circuitry:
1. From C17 through the SC1405, R13 and Q3,
returning through the phase node.
2. From C16 through the SC1405, R11/R12 and
Q4/Q5, returning through PGND.
ã 2000 Semtech Corp.
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