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SAA7108AE

HD-CODEC

Philips Electronics 

Philips Semiconductors

HD-CODEC

Product specification

SAA7108AE; SAA7109AE

8.1 Reset conditions

To activate the reset a pulse at least of 2 crystal clocks

duration is required.

During reset (RESET = LOW) plus an extra 32 crystal

clock periods, FSVGC, VSVGC, CBO, HSVGC and

TTX_SRES are set to input mode and HSM_CSYNC and

VSM are set to 3-state. A reset also forces the I2C-bus

interface to abort any running bus transfer and sets it into

receive condition.

After reset, the state of the I/Os and other functions is

defined by the strapping pins until an I2C-bus access

redefines the corresponding registers; see Table 2.

Table 2 Strapping pins

PIN

TIED

PRESET

FSVGC (pin G1)

LOW NTSC M encoding, PIXCLK

fits to 640 × 480 graphics

input

HIGH PAL B/G encoding, PIXCLK

fits to 640 × 480 graphics

input

VSVGC (pin F1) LOW 4 : 2 : 2 Y-CB-CR graphics

input (format 0)

HIGH 4 : 4 : 4 RGB graphics input

(format 3)

CBO (pin G3)

LOW input demultiplex phase:

LSB = LOW

HIGH input demultiplex phase:

LSB = HIGH

HSVGC (pin E3) LOW input demultiplex phase:

MSB = LOW

HIGH input demultiplex phase:

MSB = HIGH

TTXRQ_XCLKO2 LOW slave (FSVGC, VSVGC and

(pin C4)

HSVGC are inputs, internal

colour bar is active)

HIGH master (FSVGC, VSVGC

and HSVGC are outputs)

8.2 Input formatter

The input formatter converts all accepted PD input data

formats, either RGB or Y-CB-CR, to a common internal

RGB or Y-CB-CR data stream.

When double-edge clocking is used, the data is internally

split into portions PPD1 and PPD2. The clock edge

assignment must be set according to the I2C-bus control

bits SLOT and EDGE for correct operation.

If Y-CB-CR is being applied as a 27 Mbyte/s data stream,

the output of the input formatter can be used directly to

feed the video encoder block.

The horizontal upscaling is supported via the input

formatter. According to the programming of the pixel clock

dividers (see Section 8.10), it will upsample the data

stream to 1 ×, 2 × or 4 × the input data rate. An optional

interpolation filter is available. The clock domain transition

is handled by a 4 entries wide FIFO which gets initialized

every field or explicitly at request. A bypass for the FIFO is

available, especially for high input data rates.

8.3 RGB LUT

The three 256-byte RAMs of this block can be addressed

by three 8-bit wide signals, thus it can be used to build any

transformation, e.g. a gamma correction for RGB signals.

In the event that the indexed colour data is applied, the

RAMs are addressed in parallel.

The LUTs can either be loaded by an I2C-bus write access

or can be part of the pixel data input through the PD port.

In the latter case, 256 × 3 bytes for the R, G and B LUT are

expected at the beginning of the input video line, two lines

before the line that has been defined as first active line,

until the middle of the line immediately preceding the first

active line. The first 3 bytes represent the first RGB LUT

data, and so on.

8.4 Cursor insertion

A 32 × 32 dots cursor can be overlaid as an option; the bit

map of the cursor can be uploaded by an I2C-bus write

access to specific registers or in the pixel data input via the

PD port. In the latter case the 256 bytes defining the cursor

bit map (2 bits per pixel) are expected immediately

following the last RGB LUT data in the line preceding the

first active line.

The cursor bit map is set up as follows: each pixel

occupies 2 bits. The meaning of these bits depends on the

CMODE I2C-bus register as described in Table 5.

Transparent means that the input pixels are passed

through, the ‘cursor colours’ can be programmed in

separate registers.

The bit map is stored with 4 pixels per byte, aligned to the

least significant bit. So the first pixel is in bits 0 and 1, the

next pixel in bits 3 and 4 and so on. The first index is the

column, followed by the row; index 0,0 is the upper left

corner.

2004 Jun 29

19

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