SAA7108AE 데이터 시트보기 (PDF) - Philips Electronics

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SAA7108AE

HD-CODEC

Philips Electronics 

Philips Semiconductors

HD-CODEC

Product specification

SAA7108AE; SAA7109AE

SYMBOL

FSVGC

SDAe

CBO

PIXCLKO

VDDEd

IGPH

IGP1

ITRI

PD2

PD1

PD0

VSSEd

VSSEd

ICLK

TEST0

IDQ

TEST4

TEST5

TEST3

VDDId

VDDId

AMXCLK

ALRCLK

ITRDY

XTRI

XPD7

XPD6

VSSId

VSSId

AMCLK

RTS0

ASCLK

XPD5

XPD4

XPD3

VDDId

XRV

2004 Jun 29

PIN TYPE(1)

DESCRIPTION

G1 I/O frame synchronization output to VGC (optional input)

G2 I/O I2C-bus serial data input/output (encoder)

G3

O composite blanking output to VGC; active LOW

G4

O pixel clock output to VGC

G11 S 3.3 V digital supply voltage for peripheral cells (decoder)

G12 O multi-purpose horizontal reference output with IPD output bus

G13 O general purpose output signal 1 with IPD output bus

G14 I/(O) programmable control signals for IPD output bus

H1

I MSB − 5 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

H2

I MSB − 6 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

H3

I MSB − 7 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for

pin assignment

H4

S digital ground for peripheral cells (decoder)

H11 S digital ground for peripheral cells (decoder)

H12 I/O clock for IPD output bus (optional clock input)

H13 O scan test output, do not connect

H14 O data qualifier for IPD output bus

J1

O scan test output, do not connect

J2

I scan test input, do not connect

J3

I scan test input, do not connect

J4

S 3.3 V digital supply voltage for core (decoder)

J11

S 3.3 V digital supply voltage for core (decoder)

J12

I audio master external clock input

J13 (I/)O audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to

indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down)

has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6

J14

I target ready input for IPD output bus

K1

I control signal for all X port pins

K2 I/O MSB of XPD bus

K3 I/O MSB − 1 of XPD bus

K4

S digital ground core (decoder)

K11 S digital ground core (decoder)

K12 O audio master clock output, must be less than 50 % of crystal clock

K13 O real-time status or sync information line 0

K14 O audio serial clock output

L1

I/O MSB − 2 of XPD bus

L2

I/O MSB − 3 of XPD bus

L3

I/O MSB − 4 of XPD bus

L4

S 3.3 V digital supply voltage for core (decoder)

L5 I/O vertical reference for XPD bus

11

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