RTL8130 데이터 시트보기 (PDF) - Realtek Semiconductor
부품명
상세내역
일치하는 목록
RTL8130 Datasheet PDF : 55 Pages
| |||
RTL8130 Preliminary
11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22
33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44
55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66 + 11 22 33 44 55 66
+ MISC + CRC
4
R/W
LinkUp
Link Up:
This bit is valid when the PWEn bit of CONFIG1 register is set.
The RTL8130, in adequate power state, will assert the PMEB signal
to wakeup the operating system when the cable connection is re-
established.
3-2
R/W
Medium1,
These two bits are used to select medium mode.
Medium0
Medium mode
Medium0
0
1
Medium1
0
AutoDetect
UTP
1
MII
AUI
In AutoDetect mode, the priority is UTP > MII or UTP > AUI.
The MEDIUMWE (bit21, FLASH) should be set to 1 before
performing a config register write to these 2 bits.
1
R
MIIorAUI
1: AUI mode. The RTL8130 is configured to support UTP, AUI, and
flash.
0: MII mode. The RTL8130 is configured to support UTP and MII.
0
R
FBtBEn
Fast Back to Back Enable; Set to 1 to enable Fast Back to Back.
5.14 CONFIG 4: Configuration Register4 (Offset 005Ah, R/W)
Bit
R/W
Symbol
Description
7
-
-
Reserved.
6
-
-
Reserved.
5
R/W
LongWF
Long Wake-up Frame:
Set to 0: The RTL8139A OEM supports up to 8 wake-up frames,
each with masked bytes selected from offset 12 to 75.
Set to 1: The RTL8139A OEM supports up to 5 wake-up frames.
The wake-up frame 0 to 1 are the same as above, the wake-up frame
2 and 3 are merged into one long wake-up frame with masked bytes
selected from offset 12 to 139. So as to wakeup frame 4 and 5, 6 and
7.
4
R/W
LWPME
LANWAKE vs PMEB:
Set to 0: The LWAKE and PMEB are asserted at the same time.
Set to 1: The LWAKE can only be asserted when the PMEB is
asserted and the ISOLATEB is low.
3
R/W
MSWFB
Microsoft® Wake-up Frame: This bit is valid when the PWEn bit of
CONFIG1 register is set.
Set to 0: The RTL8130 supports Microsoft® Wake-up Frame.
Set to 1: Disable Wake-up Frame support.
2
R/W
LWPTN
LWAKE pattern: Please refer to LWACT bit in CONFIG1 register.
1
R/W
PARM_En2 Parameter Enable2: This bit is valid only when the PARM_En(bit6,
Config1) is set to 1.
Set to 0: The value of TW_PARM is auto-loaded from EEPROM
directly.
Set to 1: The value of TW_PARM is determined by twister
parameter auto-scan mechanism of the RTL8130, each time when
Link is ok in 100Mbps mode. The twister parameters used by auto-
scan mechanism are built-in in the RTL8130.
1999/5/30
20
Ver.1.1
Share Link: 