RTL8130 데이터 시트보기 (PDF) - Realtek Semiconductor
부품명
상세내역
제조사
RTL8130 Datasheet PDF : 55 Pages
| |||
15
R
14
R
13
R/W
12-0
R/W
TOK
TUN
OWN
SIZE
RTL8130 Preliminary
packet) the RTL8130 will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must be avoided from exceeding 2K byte.
Transmit OK: Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun occurs.
Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted
during the transmission of a packet. The RTL8130 can re-transfer
data if the Tx FIFO underruns and can also transmit the packet to the
wire successfully even though the Tx FIFO underruns. That is, when
TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or
ISR<TER>=1).
OWN: The RTL8130 sets this bit to 1 when the Tx DMA operation of
this descriptor was completed. The driver must set this bit to 0 when
the Transmit Byte Count (bit0-12) is written. The default value is 1.
Descriptor Size: The total size in bytes of the data in this descriptor. If
the packet length is more than 1792 byte (0700h), the Tx queue will
be invalid, i.e. the next descriptor will be written only after the OWN
bit of that long packet's descriptor has been set.
5.3 ERSR: Early Rx Status Register (Offset 0036h, R)
Bit
R/W
Symbol
Description
7-4
-
-
Reserved
3
R
ERGood
Early Rx Good packet: This bit is set whenever a packet is completely
received and the packet is good. This bit is cleared when writing 1 to
it,
2
R
ERBad
Early Rx Bad packet: This bit is set whenever a packet is completely
received and the packet is bad. Writing 1 will clear this bit.
1
R
EROVW
Early Rx OverWrite: This bit is set when the RTL8130's local address
pointer is equal to CAPR. In the early mode, this is different from
buffer overflow. It happens that the RTL8130 detected an Rx error
and wanted to fill another packet data from the beginning address of
that error packet. Writing 1 will clear this bit.
0
R
EROK
Early Rx OK: The power-on value is 0. It is set when the Rx byte
count of the arriving packet exceeds the Rx threshold. After the whole
packet is received, the RTL8130 will set ROK or RER in ISR and
clear this bit simultaneously. Setting this bit will invoke a ROK
interrupt.
5.4 Command Register (Offset 0037h, R/W)
Bit
R/W
Symbol
Description
7-5
-
-
Reserved
4
R/W
RST
Reset: Setting to 1 forces the RTL8130 to a software reset state which
disables the transmitter and receiver, reinitializes the FIFOs, resets
the system buffer pointer to the initial value (Tx buffer is at TSAD0,
Rx buffer is empty). The values of IDR0-5 and MAR0-7 and PCI
configuration space will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 by the RTL8130 when the reset
1999/5/30
12
Ver.1.1
Share Link: 