LP61L1008A 데이터 시트보기 (PDF) - AMIC Technology

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LP61L1008A

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

0V to 3.0V

3 ns

1.5V

See Figures 1 and 2

LP61L1008A

Output

ZO=50Ω

RL=50Ω

VT=1.5V

* Including scope and jig.

+3.3V

320Ω

I/O

350Ω

5pF*

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = 0°C to 70°C)

Figure 2. Output Load for tCLZ,

tOHZ, tOLZ, tCHZ, tWHZ,

and tOW

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR1

VCC for Data Retention

CE ≥ VCC - 0.2V

2

3.6

V

ICCDR1

Data Retention Current

VCC = 2V

CE ≥ VCC - 0.2V

-

3

mA

VIN ≥ VCC - 0.2V or

VIN ≤ 0.2V

tCDR

Chip Disable to Data Retention Time

0

tR

Operation Recovery Time

5

-

ns

See Retention Waveform

-

ms

PRELIMINARY (August, 2001, Version 1.0)

9

AMIC Technology, Inc.

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