LP61L1008A 데이터 시트보기 (PDF) - AMIC Technology

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LP61L1008A

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

AMIC Technology 

Read Cycle 2 (1, 3, 4, 6)

CE

DOUT

tCLZ5

tACE

Read Cycle 3 (1)

Address

OE

CE

DOUT

tRC

tAA

tOE

tOLZ5

tACE

LP61L1008A

tCHZ5

tOH

tCHZ5

Notes: 1. WE is high for Read Cycle.

2. Device is continuously enabled CE = VI.

3. Address valid prior to or coincident with CE transition low.

4. OE = VIL.

5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (August, 2001, Version 1.0)

6

AMIC Technology, Inc.

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